| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 75 const unsigned ShiftAmt = ToIdx * 16;
78 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
80 Imm &= ~(0xFFFFLL << ShiftAmt);
92 const unsigned ShiftAmt = ChunkIdx * 16;
112 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
173 unsigned ShiftAmt = 0;
176 for (; ShiftAmt < 64; ShiftAmt += 16) {
177 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
190 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
[all...] |
| AArch64ISelDAGToDAG.cpp | 239 unsigned ShiftAmt;
242 ShiftAmt = 0;
244 ShiftAmt = 12;
249 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 609 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
610 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
615 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
617 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
623 KnownZero <<= ShiftAmt;
624 KnownOne <<= ShiftAmt;
626 if (ShiftAmt)
627 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
633 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
636 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
[all...] |
| InstCombineCasts.cpp | 572 uint32_t ShiftAmt = KnownZeroMask.logBase2();
574 if (ShiftAmt) {
575 // Perform a logical shr by shiftamt.
577 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt),
712 uint64_t ShiftAmt = Amt->getZExtValue();
713 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0;
[all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 176 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1);
187 ConstantInt::get(Src->getType(), ShiftAmt));
188 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
208 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1);
213 ConstantInt::get(Src->getType(), ShiftAmt));
214 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
[all...] |
| ValueTracking.cpp | 478 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
480 KnownZero <<= ShiftAmt;
481 KnownOne <<= ShiftAmt;
482 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); // low bits known 0
490 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
494 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
495 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
497 KnownZero |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
505 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
509 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | [all...] |
| NVPTXISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | [all...] |
| AMDGPUISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 839 unsigned ShiftAmt = Shift.getConstantOperandVal(1);
840 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3)
845 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyCFG.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
