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      1 //==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file describes the subtarget options of a Target machine.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef LLVM_MC_MCSUBTARGET_H
     15 #define LLVM_MC_MCSUBTARGET_H
     16 
     17 #include "llvm/MC/MCInstrItineraries.h"
     18 #include "llvm/MC/SubtargetFeature.h"
     19 #include <string>
     20 
     21 namespace llvm {
     22 
     23 class StringRef;
     24 
     25 //===----------------------------------------------------------------------===//
     26 ///
     27 /// MCSubtargetInfo - Generic base class for all target subtargets.
     28 ///
     29 class MCSubtargetInfo {
     30   std::string TargetTriple;            // Target triple
     31   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
     32   ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
     33 
     34   // Scheduler machine model
     35   const SubtargetInfoKV *ProcSchedModels;
     36   const MCWriteProcResEntry *WriteProcResTable;
     37   const MCWriteLatencyEntry *WriteLatencyTable;
     38   const MCReadAdvanceEntry *ReadAdvanceTable;
     39   const MCSchedModel *CPUSchedModel;
     40 
     41   const InstrStage *Stages;            // Instruction itinerary stages
     42   const unsigned *OperandCycles;       // Itinerary operand cycles
     43   const unsigned *ForwardingPaths;     // Forwarding paths
     44   uint64_t FeatureBits;                // Feature bits for current CPU + FS
     45 
     46 public:
     47   void InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
     48                            ArrayRef<SubtargetFeatureKV> PF,
     49                            ArrayRef<SubtargetFeatureKV> PD,
     50                            const SubtargetInfoKV *ProcSched,
     51                            const MCWriteProcResEntry *WPR,
     52                            const MCWriteLatencyEntry *WL,
     53                            const MCReadAdvanceEntry *RA,
     54                            const InstrStage *IS,
     55                            const unsigned *OC, const unsigned *FP);
     56 
     57   /// getTargetTriple - Return the target triple string.
     58   StringRef getTargetTriple() const {
     59     return TargetTriple;
     60   }
     61 
     62   /// getFeatureBits - Return the feature bits.
     63   ///
     64   uint64_t getFeatureBits() const {
     65     return FeatureBits;
     66   }
     67 
     68   /// InitMCProcessorInfo - Set or change the CPU (optionally supplemented with
     69   /// feature string). Recompute feature bits and scheduling model.
     70   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
     71 
     72   /// InitCPUSchedModel - Recompute scheduling model based on CPU.
     73   void InitCPUSchedModel(StringRef CPU);
     74 
     75   /// ToggleFeature - Toggle a feature and returns the re-computed feature
     76   /// bits. This version does not change the implied bits.
     77   uint64_t ToggleFeature(uint64_t FB);
     78 
     79   /// ToggleFeature - Toggle a feature and returns the re-computed feature
     80   /// bits. This version will also change all implied bits.
     81   uint64_t ToggleFeature(StringRef FS);
     82 
     83   /// getSchedModelForCPU - Get the machine model of a CPU.
     84   ///
     85   const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
     86 
     87   /// getSchedModel - Get the machine model for this subtarget's CPU.
     88   ///
     89   const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
     90 
     91   /// Return an iterator at the first process resource consumed by the given
     92   /// scheduling class.
     93   const MCWriteProcResEntry *getWriteProcResBegin(
     94     const MCSchedClassDesc *SC) const {
     95     return &WriteProcResTable[SC->WriteProcResIdx];
     96   }
     97   const MCWriteProcResEntry *getWriteProcResEnd(
     98     const MCSchedClassDesc *SC) const {
     99     return getWriteProcResBegin(SC) + SC->NumWriteProcResEntries;
    100   }
    101 
    102   const MCWriteLatencyEntry *getWriteLatencyEntry(const MCSchedClassDesc *SC,
    103                                                   unsigned DefIdx) const {
    104     assert(DefIdx < SC->NumWriteLatencyEntries &&
    105            "MachineModel does not specify a WriteResource for DefIdx");
    106 
    107     return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx];
    108   }
    109 
    110   int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx,
    111                            unsigned WriteResID) const {
    112     // TODO: The number of read advance entries in a class can be significant
    113     // (~50). Consider compressing the WriteID into a dense ID of those that are
    114     // used by ReadAdvance and representing them as a bitset.
    115     for (const MCReadAdvanceEntry *I = &ReadAdvanceTable[SC->ReadAdvanceIdx],
    116            *E = I + SC->NumReadAdvanceEntries; I != E; ++I) {
    117       if (I->UseIdx < UseIdx)
    118         continue;
    119       if (I->UseIdx > UseIdx)
    120         break;
    121       // Find the first WriteResIdx match, which has the highest cycle count.
    122       if (!I->WriteResourceID || I->WriteResourceID == WriteResID) {
    123         return I->Cycles;
    124       }
    125     }
    126     return 0;
    127   }
    128 
    129   /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
    130   ///
    131   InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
    132 
    133   /// Initialize an InstrItineraryData instance.
    134   void initInstrItins(InstrItineraryData &InstrItins) const;
    135 };
    136 
    137 } // End llvm namespace
    138 
    139 #endif
    140