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    Searched refs:BLR (Results 1 - 16 of 16) sorted by null

  /external/llvm/lib/Target/AArch64/
AArch64AsmPrinter.cpp 420 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
496 MCInst BLR;
497 BLR.setOpcode(AArch64::BLR);
498 BLR.addOperand(Callee);
499 EmitToStreamer(OutStreamer, BLR);
  /external/chromium_org/v8/src/arm64/
instructions-arm64.h 310 return Mask(UnconditionalBranchToRegisterMask) == BLR;
disasm-arm64.cc 545 case BLR: mnemonic = "blr"; break;
    [all...]
assembler-arm64-inl.h 571 Emit(BLR | Rn(xzr));
601 // blr ip0
623 // blr temp
627 // blr temp
629 // The return address is immediately after the blr instruction in both cases,
840 // blr ip0
    [all...]
constants-arm64.h 615 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
    [all...]
assembler-arm64.cc 357 // blr xzr
370 // blr xzr
400 // blr xzr
404 // instruction following the offending blr.
897 // 4: blr xzr
935 Emit(BLR | Rn(xzr));
960 void Assembler::blr(const Register& xn) { function in class:v8::internal::Assembler
963 // The pattern 'blr xzr' is used as a guard to detect when execution falls
966 Emit(BLR | Rn(xn));
    [all...]
simulator-arm64.cc     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCInstrInfo.cpp     [all...]
PPCFrameLowering.cpp 822 assert((RetOpcode == PPC::BLR ||
    [all...]
PPCFastISel.cpp     [all...]
  /external/pcre/dist/sljit/
sljitNativeARM_64.c 75 #define BLR 0xd63f0000
    [all...]
sljitNativePPC_common.c 145 #define BLR (HI(19) | LO(16) | (0x14 << 21))
706 FAIL_IF(push_inst(compiler, BLR));
    [all...]
  /external/vixl/src/a64/
disasm-a64.cc 552 case BLR: mnemonic = "blr"; break;
    [all...]
constants-a64.h 505 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
    [all...]
assembler-a64.cc 437 void Assembler::blr(const Register& xn) { function in class:vixl::Assembler
439 Emit(BLR | Rn(xn));
    [all...]
simulator-a64.cc 546 case BLR:
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