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      1 //===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the SPARC implementation of the TargetRegisterInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "SparcRegisterInfo.h"
     15 #include "Sparc.h"
     16 #include "SparcMachineFunctionInfo.h"
     17 #include "SparcSubtarget.h"
     18 #include "llvm/ADT/BitVector.h"
     19 #include "llvm/ADT/STLExtras.h"
     20 #include "llvm/CodeGen/MachineFrameInfo.h"
     21 #include "llvm/CodeGen/MachineFunction.h"
     22 #include "llvm/CodeGen/MachineInstrBuilder.h"
     23 #include "llvm/IR/Type.h"
     24 #include "llvm/Support/CommandLine.h"
     25 #include "llvm/Support/ErrorHandling.h"
     26 #include "llvm/Target/TargetInstrInfo.h"
     27 
     28 using namespace llvm;
     29 
     30 #define GET_REGINFO_TARGET_DESC
     31 #include "SparcGenRegisterInfo.inc"
     32 
     33 static cl::opt<bool>
     34 ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
     35                     cl::desc("Reserve application registers (%g2-%g4)"));
     36 
     37 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
     38   : SparcGenRegisterInfo(SP::O7), Subtarget(st) {
     39 }
     40 
     41 const MCPhysReg*
     42 SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
     43   return CSR_SaveList;
     44 }
     45 
     46 const uint32_t*
     47 SparcRegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
     48   return CSR_RegMask;
     49 }
     50 
     51 const uint32_t*
     52 SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
     53   return RTCSR_RegMask;
     54 }
     55 
     56 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     57   BitVector Reserved(getNumRegs());
     58   // FIXME: G1 reserved for now for large imm generation by frame code.
     59   Reserved.set(SP::G1);
     60 
     61   // G1-G4 can be used in applications.
     62   if (ReserveAppRegisters) {
     63     Reserved.set(SP::G2);
     64     Reserved.set(SP::G3);
     65     Reserved.set(SP::G4);
     66   }
     67   // G5 is not reserved in 64 bit mode.
     68   if (!Subtarget.is64Bit())
     69     Reserved.set(SP::G5);
     70 
     71   Reserved.set(SP::O6);
     72   Reserved.set(SP::I6);
     73   Reserved.set(SP::I7);
     74   Reserved.set(SP::G0);
     75   Reserved.set(SP::G6);
     76   Reserved.set(SP::G7);
     77 
     78   // Unaliased double registers are not available in non-V9 targets.
     79   if (!Subtarget.isV9()) {
     80     for (unsigned n = 0; n != 16; ++n) {
     81       for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
     82         Reserved.set(*AI);
     83     }
     84   }
     85 
     86   return Reserved;
     87 }
     88 
     89 const TargetRegisterClass*
     90 SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
     91                                       unsigned Kind) const {
     92   return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
     93 }
     94 
     95 static void replaceFI(MachineFunction &MF,
     96                       MachineBasicBlock::iterator II,
     97                       MachineInstr &MI,
     98                       DebugLoc dl,
     99                       unsigned FIOperandNum, int Offset,
    100                       unsigned FramePtr)
    101 {
    102   // Replace frame index with a frame pointer reference.
    103   if (Offset >= -4096 && Offset <= 4095) {
    104     // If the offset is small enough to fit in the immediate field, directly
    105     // encode it.
    106     MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
    107     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
    108     return;
    109   }
    110 
    111   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    112 
    113   // FIXME: it would be better to scavenge a register here instead of
    114   // reserving G1 all of the time.
    115   if (Offset >= 0) {
    116     // Emit nonnegaive immediates with sethi + or.
    117     // sethi %hi(Offset), %g1
    118     // add %g1, %fp, %g1
    119     // Insert G1+%lo(offset) into the user.
    120     BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
    121       .addImm(HI22(Offset));
    122 
    123 
    124     // Emit G1 = G1 + I6
    125     BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
    126       .addReg(FramePtr);
    127     // Insert: G1+%lo(offset) into the user.
    128     MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
    129     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
    130     return;
    131   }
    132 
    133   // Emit Negative numbers with sethi + xor
    134   // sethi %hix(Offset), %g1
    135   // xor  %g1, %lox(offset), %g1
    136   // add %g1, %fp, %g1
    137   // Insert: G1 + 0 into the user.
    138   BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
    139     .addImm(HIX22(Offset));
    140   BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
    141     .addReg(SP::G1).addImm(LOX10(Offset));
    142 
    143   BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
    144     .addReg(FramePtr);
    145   // Insert: G1+%lo(offset) into the user.
    146   MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
    147   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
    148 }
    149 
    150 
    151 void
    152 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
    153                                        int SPAdj, unsigned FIOperandNum,
    154                                        RegScavenger *RS) const {
    155   assert(SPAdj == 0 && "Unexpected");
    156 
    157   MachineInstr &MI = *II;
    158   DebugLoc dl = MI.getDebugLoc();
    159   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
    160 
    161   // Addressable stack objects are accessed using neg. offsets from %fp
    162   MachineFunction &MF = *MI.getParent()->getParent();
    163   int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
    164                    MI.getOperand(FIOperandNum + 1).getImm() +
    165                    Subtarget.getStackPointerBias();
    166   SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
    167   unsigned FramePtr = SP::I6;
    168   if (FuncInfo->isLeafProc()) {
    169     // Use %sp and adjust offset if needed.
    170     FramePtr = SP::O6;
    171     int stackSize = MF.getFrameInfo()->getStackSize();
    172     Offset += (stackSize) ? Subtarget.getAdjustedFrameSize(stackSize) : 0 ;
    173   }
    174 
    175   if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
    176     if (MI.getOpcode() == SP::STQFri) {
    177       const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    178       unsigned SrcReg = MI.getOperand(2).getReg();
    179       unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
    180       unsigned SrcOddReg  = getSubReg(SrcReg, SP::sub_odd64);
    181       MachineInstr *StMI =
    182         BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
    183         .addReg(FramePtr).addImm(0).addReg(SrcEvenReg);
    184       replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr);
    185       MI.setDesc(TII.get(SP::STDFri));
    186       MI.getOperand(2).setReg(SrcOddReg);
    187       Offset += 8;
    188     } else if (MI.getOpcode() == SP::LDQFri) {
    189       const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
    190       unsigned DestReg     = MI.getOperand(0).getReg();
    191       unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
    192       unsigned DestOddReg  = getSubReg(DestReg, SP::sub_odd64);
    193       MachineInstr *StMI =
    194         BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
    195         .addReg(FramePtr).addImm(0);
    196       replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr);
    197 
    198       MI.setDesc(TII.get(SP::LDDFri));
    199       MI.getOperand(0).setReg(DestOddReg);
    200       Offset += 8;
    201     }
    202   }
    203 
    204   replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FramePtr);
    205 
    206 }
    207 
    208 unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
    209   return SP::I6;
    210 }
    211 
    212