| /external/chromium_org/third_party/skia/src/core/ |
| SkChecksum.h | 29 ROTR = 17,
30 ROTL = sizeof(uintptr_t) * 8 - ROTR,
35 return ((total >> ROTR) | (total << ROTL)) ^ value;
|
| /external/skia/include/core/ |
| SkChecksum.h | 29 ROTR = 17,
30 ROTL = sizeof(uintptr_t) * 8 - ROTR,
35 return ((total >> ROTR) | (total << ROTL)) ^ value;
|
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 29 case ISD::ROTR: return ARM_AM::ror;
30 //case ISD::ROTL: // Only if imm -> turn into ROTR.
|
| /external/chromium_org/third_party/boringssl/src/crypto/sha/ |
| sha512.c | 344 #define ROTR(a, n) \
365 #define ROTR(a, n) \
372 #define ROTR(a, n) \
391 #define ROTR(a, n) _rotr64((a), n)
415 #ifndef ROTR
416 #define ROTR(x, s) (((x) >> s) | (x) << (64 - s))
419 #define Sigma0(x) (ROTR((x), 28) ^ ROTR((x), 34) ^ ROTR((x), 39))
420 #define Sigma1(x) (ROTR((x), 14) ^ ROTR((x), 18) ^ ROTR((x), 41)
[all...] |
| /external/openssl/crypto/sha/ |
| sha512.c | 316 # define ROTR(a,n) ({ SHA_LONG64 ret; \
346 # define ROTR(a,n) ({ SHA_LONG64 ret; \
354 # define ROTR(a,n) _rotr64((a),n)
389 #ifndef ROTR
390 #define ROTR(x,s) (((x)>>s) | (x)<<(64-s))
393 #define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
394 #define Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41)
[all...] |
| /external/chromium_org/third_party/boringssl/src/crypto/sha/asm/ |
| sha512-armv4.pl | 92 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
147 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
324 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
341 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)
[all...] |
| /external/openssl/crypto/sha/asm/ |
| sha512-armv4.pl | 75 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
130 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
305 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
322 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)
[all...] |
| sha512-armv4.S | 131 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
186 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
225 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
242 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)
[all...] |
| /external/pdfium/core/src/fdrm/crypto/ |
| fx_crypt_sha.cpp | 219 #define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))
220 #define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^ SHR(x, 3))
221 #define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^ SHR(x,10))
222 #define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))
223 #define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 311 SHL, SRA, SRL, ROTL, ROTR,
[all...] |
| /external/valgrind/main/none/tests/mips64/ |
| shift_instructions.c | 9 ROTR, ROTRV, SLL, SLLV,
143 case ROTR:
146 TEST2("rotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
147 TEST2("rotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
148 TEST2("rotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
149 TEST2("rotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
|
| /external/chromium_org/third_party/boringssl/linux-arm/crypto/sha/ |
| sha512-armv4.S | 133 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
188 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
227 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
244 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6)
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 401 mMips->ROTR(tmpReg, amode.reg, amode.value);
512 mMips->ROTR(Rd, amode.reg, amode.value);
544 mMips->ROTR(Rd, amode.reg, amode.value);
[all...] |
| MIPSAssembler.h | 319 void ROTR(int Rd, int Rt, int shft); // mips32r2
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 144 setOperationAction(ISD::ROTR, MVT::i32, Expand);
145 setOperationAction(ISD::ROTR, MVT::i64, Expand);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 181 case ISD::ROTR: return "rotr";
|
| LegalizeVectorOps.cpp | 257 case ISD::ROTR:
[all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 166 setOperationAction(ISD::ROTR, MVT::i64, Legal);
169 setOperationAction(ISD::ROTR, MVT::i64, Expand);
173 setOperationAction(ISD::ROTR, MVT::i32, Legal);
176 setOperationAction(ISD::ROTR, MVT::i32, Expand);
180 setOperationAction(ISD::ROTR, MVT::i16, Expand);
182 setOperationAction(ISD::ROTR, MVT::i8, Expand);
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 99 setOperationAction(ISD::ROTR, MVT::i8, Expand);
101 setOperationAction(ISD::ROTR, MVT::i16, Expand);
[all...] |
| /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 151 // GPU doesn't have a rotl, rotr, or byteswap instruction
152 setOperationAction(ISD::ROTR, VT, Expand);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 151 // GPU doesn't have a rotl, rotr, or byteswap instruction
152 setOperationAction(ISD::ROTR, VT, Expand);
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 269 // The hardware supports 32-bit ROTR, but not ROTL.
272 setOperationAction(ISD::ROTR, MVT::i64, Expand);
299 setOperationAction(ISD::ROTR, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
