| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 535 BinaryOperator *ShiftOp = dyn_cast<BinaryOperator>(Op0);
536 if (ShiftOp && !ShiftOp->isShift())
537 ShiftOp = nullptr;
539 if (ShiftOp && isa<ConstantInt>(ShiftOp->getOperand(1))) {
553 ConstantInt *ShiftAmt1C = cast<ConstantInt>(ShiftOp->getOperand(1));
558 Value *X = ShiftOp->getOperand(0);
563 if (I.getOpcode() == ShiftOp->getOpcode()) {
580 ShiftOp->getOpcode() == Instruction::Shl)
[all...] |
| /external/chromium_org/v8/src/arm/ |
| constants-arm.h | 228 enum ShiftOp {
235 // Use a special code to make the distinction. The RRX ShiftOp is only used
558 inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); }
559 inline ShiftOp ShiftField() const {
560 return static_cast<ShiftOp>(BitField(6, 5));
|
| assembler-arm.h | 502 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
516 explicit Operand(Register rm, ShiftOp shift_op, Register rs);
542 ShiftOp shift_op() const { return shift_op_; }
547 ShiftOp shift_op_;
575 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
605 ShiftOp shift_op_;
[all...] |
| disasm-arm.cc | 191 ShiftOp shift = instr->ShiftField();
[all...] |
| assembler-arm.cc | 281 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) {
302 Operand::Operand(Register rm, ShiftOp shift_op, Register rs) {
329 ShiftOp shift_op, int shift_imm, AddrMode am) {
[all...] |
| simulator-arm.cc | [all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 723 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
724 bool isASR = (ShiftOp & (1 << 5)) != 0;
725 unsigned Amt = ShiftOp & 0x1f;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
