/external/llvm/lib/Target/Hexagon/ |
HexagonSplitTFRCondSets.cpp | 100 int SrcReg2 = MI->getOperand(3).getReg(); 118 if (DestReg != SrcReg2) { 120 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 157 int SrcReg2 = MI->getOperand(3).getReg(); 173 if (DestReg != SrcReg2) { 176 addReg(MI->getOperand(1).getReg()).addReg(SrcReg2);
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HexagonInstrInfo.h | 75 unsigned &SrcReg, unsigned &SrcReg2,
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HexagonInstrInfo.cpp | 339 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it 343 unsigned &SrcReg, unsigned &SrcReg2, 397 SrcReg2 = MI->getOperand(2).getReg(); 407 SrcReg2 = 0; [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZElimCompare.cpp | 382 unsigned SrcReg2 = (Compare->getOperand(1).isReg() ? 387 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) 413 // Clear any intervening kills of SrcReg and SrcReg2. 417 if (SrcReg2) 418 MBBI->clearRegisterKills(SrcReg2, TRI);
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SystemZInstrInfo.h | 153 unsigned &SrcReg2, int &Mask, int &Value) const override; 155 unsigned SrcReg2, int Mask, int Value,
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SystemZInstrInfo.cpp | 400 unsigned &SrcReg, unsigned &SrcReg2, 408 SrcReg2 = 0; 484 unsigned SrcReg, unsigned SrcReg2, 487 assert(!SrcReg2 && "Only optimizing constant comparisons so far"); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.h | 148 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue. 151 unsigned &SrcReg2, int &CmpMask, 156 unsigned SrcReg2, int CmpMask, int CmpValue,
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AArch64FastISel.cpp | 952 unsigned SrcReg2; 954 SrcReg2 = getRegForValue(Src2Value); 955 if (SrcReg2 == 0) 965 SrcReg2 = EmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); 966 if (SrcReg2 == 0) 982 .addReg(SrcReg2); [all...] |
AArch64InstrInfo.cpp | 610 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue. 613 unsigned &SrcReg2, int &CmpMask, 632 SrcReg2 = MI->getOperand(2).getReg(); 641 SrcReg2 = 0; 650 SrcReg2 = 0; 703 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, 741 if (CmpValue != 0 || SrcReg2 != 0) [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCInstrInfo.h | 219 unsigned &SrcReg, unsigned &SrcReg2, 223 unsigned SrcReg, unsigned SrcReg2,
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PPCFastISel.cpp | 796 unsigned SrcReg2 = 0; 798 SrcReg2 = getRegForValue(SrcValue2); 799 if (SrcReg2 == 0) 811 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt)) 813 SrcReg2 = ExtReg; 819 .addReg(SrcReg1).addReg(SrcReg2); [all...] |
PPCInstrInfo.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 424 /// in SrcReg and SrcReg2 if having two register operands, and the value it 428 unsigned &SrcReg2, int &CmpMask, 435 unsigned SrcReg2, int CmpMask, int CmpValue,
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X86InstrInfo.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
PeepholeOptimizer.cpp | 417 unsigned SrcReg, SrcReg2; 419 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || 421 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2))) 425 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) { [all...] |
/external/llvm/include/llvm/Target/ |
TargetInstrInfo.h | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.h | 185 /// in SrcReg and SrcReg2 if having two register operands, and the value it 189 unsigned &SrcReg2, int &CmpMask, 197 unsigned SrcReg2, int CmpMask, int CmpValue,
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ARMFastISel.cpp | [all...] |
ARMBaseInstrInfo.cpp | [all...] |
/external/chromium_org/third_party/mesa/src/src/gallium/drivers/r300/compiler/ |
radeon_program_alu.c | 83 struct rc_src_register SrcReg2) 95 fpi->U.I.SrcReg[2] = SrcReg2; [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_program_alu.c | 83 struct rc_src_register SrcReg2) 95 fpi->U.I.SrcReg[2] = SrcReg2; [all...] |