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    Searched refs:getSchedClass (Results 1 - 19 of 19) sorted by null

  /external/llvm/lib/CodeGen/
DFAPacketizer.cpp 67 unsigned InsnClass = MID->getSchedClass();
79 unsigned InsnClass = MID->getSchedClass();
ScoreboardHazardRecognizer.cpp 134 unsigned idx = MCID->getSchedClass();
194 unsigned idx = MCID->getSchedClass();
TargetSchedule.cpp 80 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
106 unsigned SchedClass = MI->getDesc().getSchedClass();
169 unsigned DefClass = DefMI->getDesc().getSchedClass();
TargetInstrInfo.cpp 710 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
713 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
725 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
738 unsigned Class = MI->getDesc().getSchedClass();
773 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
782 unsigned DefClass = DefMI->getDesc().getSchedClass();
793 unsigned DefClass = DefMI->getDesc().getSchedClass();
794 unsigned UseClass = UseMI->getDesc().getSchedClass();
841 unsigned DefClass = DefMI->getDesc().getSchedClass();
MachineScheduler.cpp     [all...]
ScheduleDAGInstrs.cpp 712 const MCSchedClassDesc *SC = getSchedClass(SU);
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64StorePairSuppress.cpp 82 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCInst.cpp 26 IS = II->beginStage(QII->get(this->getOpcode()).getSchedClass());
  /external/llvm/include/llvm/CodeGen/
ScheduleDAGInstrs.h 174 const MCSchedClassDesc *getSchedClass(SUnit *SU) const {
  /external/llvm/lib/MC/MCDisassembler/
Disassembler.cpp 189 unsigned SCClass = Desc.getSchedClass();
216 unsigned SCClass = Desc.getSchedClass();
  /external/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
92 unsigned IIC = MCID->getSchedClass();
  /external/llvm/utils/TableGen/
CodeGenSchedule.h 340 CodeGenSchedClass &getSchedClass(unsigned Idx) {
344 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
SubtargetEmitter.cpp 600 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
    [all...]
CodeGenSchedule.cpp 547 CodeGenSchedClass &SC = getSchedClass(SCIdx);
    [all...]
  /external/llvm/include/llvm/MC/
MCInstrDesc.h 576 unsigned getSchedClass() const {
  /external/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp     [all...]
ARMISelLowering.cpp     [all...]
  /external/llvm/lib/Target/R600/
R600InstrInfo.cpp 188 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
196 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonVLIWPacketizer.cpp     [all...]

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