| /bionic/libc/arch-arm64/generic/bionic/ |
| strchr.S | 96 cmeq vhas_nul1.16b, vdata1.16b, #0
97 cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
98 cmeq vhas_nul2.16b, vdata2.16b, #0
99 cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
118 cmeq vhas_nul1.16b, vdata1.16b, #0
119 cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
120 cmeq vhas_nul2.16b, vdata2.16b, #0
121 cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
|
| memchr.S | 98 cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
99 cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
117 cmeq vhas_chr1.16b, vdata1.16b, vrepchr.16b
118 cmeq vhas_chr2.16b, vdata2.16b, vrepchr.16b
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vselect.ll | 4 ;CHECK: cmeq.4h v0, v0, v1
|
| arm64-neon-select_cc.ll | 7 ; CHECK: cmeq [[MASK:v[0-9]+]].8b, v[[LHS]].8b, v[[RHS]].8b
38 ; CHECK: cmeq [[MASK:v[0-9]+]].16b, v[[LHS]].16b, v[[RHS]].16b
70 ; CHECK: cmeq [[MASK:v[0-9]+]].4h, v[[LHS]].4h, v[[RHS]].4h
82 ; CHECK: cmeq [[MASK:v[0-9]+]].8h, v[[LHS]].8h, v[[RHS]].8h
94 ; CHECK: cmeq [[MASK:v[0-9]+]].2s, v[[LHS]].2s, v[[RHS]].2s
106 ; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s
118 ; CHECK: cmeq d[[MASK:[0-9]+]], d[[LHS]], d[[RHS]]
129 ; CHECK: cmeq [[MASK:v[0-9]+]].2d, v[[LHS]].2d, v[[RHS]].2d
170 ; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s
191 ; CHECK: cmeq d[[MASK:[0-9]+]], [[LHS]], [[RHS]
[all...] |
| aarch64-neon-v1i1-setcc.ll | 32 ; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
50 ; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
|
| arm64-neon-v1i1-setcc.ll | 28 ; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
46 ; CHECK: cmeq d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
|
| arm64-neon-compare-instructions.ll | 4 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
11 ;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
18 ;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
25 ;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
32 ;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
39 ;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
46 ;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
53 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
61 ;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
69 ;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4
[all...] |
| neon-compare-instructions.ll | 5 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
13 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
21 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
29 ; CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
37 ; CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
45 ; CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
53 ; CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
61 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
70 ; CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
79 ; CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4
[all...] |
| arm64-vcmp.ll | 231 ; CHECK: cmeq d[[EQ:[0-9]+]], d0, #0
|
| neon-shift-left-long.ll | 197 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
|
| neon-bitwise-instructions.ll | 662 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
672 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
681 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
691 ; CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-compare-instructions.s | 9 cmeq v0.8b, v15.8b, v17.8b
10 cmeq v1.16b, v31.16b, v8.16b
11 cmeq v15.4h, v16.4h, v17.4h
12 cmeq v5.8h, v6.8h, v7.8h
13 cmeq v29.2s, v27.2s, v28.2s
14 cmeq v9.4s, v7.4s, v8.4s
15 cmeq v3.2d, v31.2d, v21.2d
17 // CHECK: cmeq v0.8b, v15.8b, v17.8b // encoding: [0xe0,0x8d,0x31,0x2e]
18 // CHECK: cmeq v1.16b, v31.16b, v8.16b // encoding: [0xe1,0x8f,0x28,0x6e]
19 // CHECK: cmeq v15.4h, v16.4h, v17.4h // encoding: [0x0f,0x8e,0x71,0x2e
[all...] |
| neon-scalar-compare.s | 9 cmeq d20, d21, d22
11 // CHECK: cmeq d20, d21, d22 // encoding: [0xb4,0x8e,0xf6,0x7e]
17 cmeq d20, d21, #0x0
19 // CHECK: cmeq d20, d21, #{{0x0|0}} // encoding: [0xb4,0x9a,0xe0,0x5e]
|
| arm64-advsimd.s | 302 cmeq.8b v0, v0, v0
372 ; CHECK: cmeq.8b v0, v0, v0 ; encoding: [0x00,0x8c,0x20,0x2e]
572 cmeq.8b v0, v0, #0
573 cmeq.16b v0, v0, #0
574 cmeq.4h v0, v0, #0
575 cmeq.8h v0, v0, #0
576 cmeq.2s v0, v0, #0
577 cmeq.4s v0, v0, #0
578 cmeq.2d v0, v0, #0
580 ; CHECK: cmeq.8b v0, v0, #0 ; encoding: [0x00,0x98,0x20,0x0e
[all...] |
| neon-diagnostics.s | 451 cmeq c0.2d, v1.2d, v2.2s
454 // CHECK-ERROR: cmeq c0.2d, v1.2d, v2.2s
603 cmeq c0.2d, v1.2s, #0
604 cmeq c0.2d, v1.2d, #1
607 // CHECK-ERROR: cmeq c0.2d, v1.2s, #0
610 // CHECK-ERROR: cmeq c0.2d, v1.2d, #1
[all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-misc.c | 10 // CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x0|0}}
16 // CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #{{0x0|0}}
22 // CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #{{0x0|0}}
28 // CHECK: cmeq {{d[0-9]+}}, {{d[0-9]+}}, #{{0x0|0}}
34 // CHECK: cmeq {{d[0-9]+}}, {{d[0-9]+}}, #{{0x0|0}}
40 // CHECK: cmeq {{d[0-9]+}}, {{d[0-9]+}}, #{{0x0|0}}
46 // CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x0|0}}
52 // CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #{{0x0|0}}
58 // CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #{{0x0|0}}
64 // CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #{{0x0|0}
[all...] |
| aarch64-poly64.c | 13 // CHECK: cmeq {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
19 // CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
|
| aarch64-neon-intrinsics.c | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 122 CMEQ,
|
| AArch64InstrInfo.td | 193 def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>;
[all...] |
| AArch64ISelLowering.cpp | 702 case AArch64ISD::CMEQ: return "AArch64ISD::CMEQ";
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | 250 # CHECK: cmeq.8b v0, v0, v0
479 # CHECK: cmeq.8b v0, v0, #0
480 # CHECK: cmeq.16b v0, v0, #0
481 # CHECK: cmeq.4h v0, v0, #0
482 # CHECK: cmeq.8h v0, v0, #0
483 # CHECK: cmeq.2s v0, v0, #0
484 # CHECK: cmeq.4s v0, v0, #0
485 # CHECK: cmeq.2d v0, v0, #0
[all...] |
| /external/valgrind/main/none/tests/arm64/ |
| fp_and_simd.c | 960 GEN_BINARY_TEST(cmeq, 2d, 2d, 2d)
961 GEN_BINARY_TEST(cmeq, 4s, 4s, 4s)
962 GEN_BINARY_TEST(cmeq, 2s, 2s, 2s)
963 GEN_BINARY_TEST(cmeq, 8h, 8h, 8h)
964 GEN_BINARY_TEST(cmeq, 4h, 4h, 4h)
965 GEN_BINARY_TEST(cmeq, 16b, 16b, 16b)
966 GEN_BINARY_TEST(cmeq, 8b, 8b, 8b)
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_arm64_defs.c | 890 case ARM64vecb_CMEQ64x2: *nm = "cmeq"; *ar = "2d"; return;
891 case ARM64vecb_CMEQ32x4: *nm = "cmeq"; *ar = "4s"; return;
892 case ARM64vecb_CMEQ16x8: *nm = "cmeq"; *ar = "8h"; return;
893 case ARM64vecb_CMEQ8x16: *nm = "cmeq"; *ar = "16b"; return;
[all...] |
| /external/clang/include/clang/Basic/ |
| arm_neon.td | [all...] |
