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  /art/disassembler/
disassembler_arm.cc 114 "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror",
119 "lsl", "lsr", "asr", "ror"
668 // TODO: use canonical form if there is a shift (lsl, ...).
740 case 0x0: args << "lsl"; break;
    [all...]
  /art/compiler/utils/arm/
assembler_arm32.h 200 void Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc = false,
211 void Lsl(Register rd, Register rm, Register rn, bool setcc = false,
  /bionic/libc/arch-arm/cortex-a15/bionic/
strcmp.S 33 #define S2LOMEM lsl
45 #define S2HIMEM lsl
  /external/chromium_org/third_party/freetype/include/freetype/config/
ftconfig.h 360 orr a, a, t, lsl #16 /* a |= t << 16 */
390 "orr %0, %0, %2, lsl #16\n\t" /* %0 |= %2 << 16 */
  /external/libhevc/common/arm/
ihevc_sao_band_offset_chroma.s 103 LSL r6,r5,#3 @sao_band_pos_u
152 LSL r11,r6,#3 @sao_band_pos_v
ihevc_inter_pred_chroma_copy.s 108 lsl r12,r12,#1
ihevc_itrans_recon_4x4.s 143 add r10,r9,r4, lsl #1 @ 3*src_strd
ihevc_sao_band_offset_luma.s 96 LSL r11,r5,#3
  /external/libhevc/common/arm64/
ihevc_sao_edge_offset_class2_chroma.s 414 LSL x4,x4,#1 //I (ht_tmp - row) * 2
486 ADD x8,x0,x1,LSL #1 //II *pu1_src + src_strd
509 LSL x5,x5,#1 //II (ht_tmp - row) * 2
549 LSL x5,x5,#1 //III (ht_tmp - row) * 2
    [all...]
ihevc_inter_pred_chroma_copy.s 103 LSL x12,x6,#1 //wd << 1
  /external/libvpx/libvpx/vp8/common/arm/neon/
buildintrapredictorsmby_neon.asm 123 add r12, r12, r5, lsl r4
406 add r12, r12, r5, lsl r4
idct_dequant_full_2x_neon.asm 169 sub r2, r2, r3, lsl #2 ; dst - 4*stride
  /external/pdfium/core/include/thirdparties/freetype/freetype/config/
ftconfig.h 361 orr a, a, t, lsl #16 /* a |= t << 16 */
391 "orr %0, %0, %2, lsl #16\n\t" /* %0 |= %2 << 16 */
  /external/pdfium/core/src/fxge/fx_freetype/fxft2.5.01/include/freetype/config/
ftconfig.h 361 orr a, a, t, lsl #16 /* a |= t << 16 */
391 "orr %0, %0, %2, lsl #16\n\t" /* %0 |= %2 << 16 */
  /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/
omxVCM4P2_MCReconBlock_s.s 367 ADD predictType, rndVal, predictType, LSL #1
405 SUBNE pDst, pDst, dstStep, LSL #3 ;// Restoring pDst
  /frameworks/rs/cpu_ref/
rsCpuIntrinsics_advsimd_3DLUT.S 167 bic v0.8h, #0xff, LSL #8
169 bic v2.8h, #0xff, LSL #8
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/
buildintrapredictorsmby_neon.asm 123 add r12, r12, r5, lsl r4
406 add r12, r12, r5, lsl r4
  /hardware/ti/omap4-aah/camera/
Encoder_libjpeg.cpp 149 " pld [%[src], %[src_stride], lsl #2] \n\t"
204 " pld [%[src], %[src_stride], lsl #2] \n\t"
  /external/chromium_org/v8/src/arm/
lithium-codegen-arm.cc     [all...]
  /external/chromium_org/third_party/openmax_dl/dl/sp/src/arm/neon/
omxSP_FFTInv_CCSToR_S16_Sfs_s.S 157 ADD pSrc,pOut,N,LSL #2 @ set pSrc as pOut1
  /external/chromium_org/third_party/webrtc/common_audio/signal_processing/
downsample_fast_neon.S 80 lsl r5, #1 @ r5 = factor * sizeof(data_in)
  /external/llvm/lib/Target/AArch64/
AArch64SchedCyclone.td 153 // EXAMPLE: ADDrs Xn, Xm LSL #imm
238 // EXAMPLE: LDR Xn, Xm [, lsl 3]
244 // EXAMPLE: STR Xn, Xm [, lsl 3]
251 // EXAMPLE: LDR Xn, Xm [, lsl 3]
  /external/llvm/test/CodeGen/AArch64/
arm64-register-offset-addressing.ll 5 ; CHECK: lsl [[REG:x[0-9]+]], x1, #1
complex-int-to-fp.ll 158 ; CHECK: bic.4h v0, #0xff, lsl #8
  /external/openssl/crypto/sha/asm/
sha256-armv4.pl 80 orr $t1,$t1,$t2,lsl#8
82 orr $t1,$t1,$t0,lsl#16
87 orr $t1,$t1,$t2,lsl#24
188 add $len,$inp,$len,lsl#6 @ len to point at the end of inp

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