1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s 2 3 ; CHECK: autogen_SD19655 4 ; CHECK: scvtf 5 ; CHECK: ret 6 define void @autogen_SD19655(<2 x i64>* %addr, <2 x float>* %addrfloat) { 7 %T = load <2 x i64>* %addr 8 %F = sitofp <2 x i64> %T to <2 x float> 9 store <2 x float> %F, <2 x float>* %addrfloat 10 ret void 11 } 12 13 define <2 x double> @test_signed_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone { 14 ; CHECK-LABEL: test_signed_v2i32_to_v2f64: 15 ; CHECK: sshll.2d [[VAL64:v[0-9]+]], v0, #0 16 ; CHECK-NEXT: scvtf.2d v0, [[VAL64]] 17 ; CHECK-NEXT: ret 18 %conv = sitofp <2 x i32> %v to <2 x double> 19 ret <2 x double> %conv 20 } 21 22 define <2 x double> @test_unsigned_v2i32_to_v2f64(<2 x i32> %v) nounwind readnone { 23 ; CHECK-LABEL: test_unsigned_v2i32_to_v2f64 24 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0 25 ; CHECK-NEXT: ucvtf.2d v0, [[VAL64]] 26 ; CHECK-NEXT: ret 27 %conv = uitofp <2 x i32> %v to <2 x double> 28 ret <2 x double> %conv 29 } 30 31 define <2 x double> @test_signed_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone { 32 ; CHECK-LABEL: test_signed_v2i16_to_v2f64: 33 ; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16 34 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16 35 ; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0 36 ; CHECK: scvtf.2d v0, [[VAL64]] 37 38 %conv = sitofp <2 x i16> %v to <2 x double> 39 ret <2 x double> %conv 40 } 41 define <2 x double> @test_unsigned_v2i16_to_v2f64(<2 x i16> %v) nounwind readnone { 42 ; CHECK-LABEL: test_unsigned_v2i16_to_v2f64 43 ; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff 44 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]] 45 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0 46 ; CHECK: ucvtf.2d v0, [[VAL64]] 47 48 %conv = uitofp <2 x i16> %v to <2 x double> 49 ret <2 x double> %conv 50 } 51 52 define <2 x double> @test_signed_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone { 53 ; CHECK-LABEL: test_signed_v2i8_to_v2f64: 54 ; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24 55 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24 56 ; CHECK: sshll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0 57 ; CHECK: scvtf.2d v0, [[VAL64]] 58 59 %conv = sitofp <2 x i8> %v to <2 x double> 60 ret <2 x double> %conv 61 } 62 define <2 x double> @test_unsigned_v2i8_to_v2f64(<2 x i8> %v) nounwind readnone { 63 ; CHECK-LABEL: test_unsigned_v2i8_to_v2f64 64 ; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff 65 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]] 66 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0 67 ; CHECK: ucvtf.2d v0, [[VAL64]] 68 69 %conv = uitofp <2 x i8> %v to <2 x double> 70 ret <2 x double> %conv 71 } 72 73 define <2 x float> @test_signed_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone { 74 ; CHECK-LABEL: test_signed_v2i64_to_v2f32: 75 ; CHECK: scvtf.2d [[VAL64:v[0-9]+]], v0 76 ; CHECK: fcvtn v0.2s, [[VAL64]].2d 77 78 %conv = sitofp <2 x i64> %v to <2 x float> 79 ret <2 x float> %conv 80 } 81 define <2 x float> @test_unsigned_v2i64_to_v2f32(<2 x i64> %v) nounwind readnone { 82 ; CHECK-LABEL: test_unsigned_v2i64_to_v2f32 83 ; CHECK: ucvtf.2d [[VAL64:v[0-9]+]], v0 84 ; CHECK: fcvtn v0.2s, [[VAL64]].2d 85 86 %conv = uitofp <2 x i64> %v to <2 x float> 87 ret <2 x float> %conv 88 } 89 90 define <2 x float> @test_signed_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone { 91 ; CHECK-LABEL: test_signed_v2i16_to_v2f32: 92 ; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #16 93 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #16 94 ; CHECK: scvtf.2s v0, [[VAL32]] 95 96 %conv = sitofp <2 x i16> %v to <2 x float> 97 ret <2 x float> %conv 98 } 99 define <2 x float> @test_unsigned_v2i16_to_v2f32(<2 x i16> %v) nounwind readnone { 100 ; CHECK-LABEL: test_unsigned_v2i16_to_v2f32 101 ; CHECK: movi d[[MASK:[0-9]+]], #0x00ffff0000ffff 102 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]] 103 ; CHECK: ucvtf.2s v0, [[VAL32]] 104 105 %conv = uitofp <2 x i16> %v to <2 x float> 106 ret <2 x float> %conv 107 } 108 109 define <2 x float> @test_signed_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone { 110 ; CHECK-LABEL: test_signed_v2i8_to_v2f32: 111 ; CHECK: shl.2s [[TMP:v[0-9]+]], v0, #24 112 ; CHECK: sshr.2s [[VAL32:v[0-9]+]], [[TMP]], #24 113 ; CHECK: scvtf.2s v0, [[VAL32]] 114 115 %conv = sitofp <2 x i8> %v to <2 x float> 116 ret <2 x float> %conv 117 } 118 define <2 x float> @test_unsigned_v2i8_to_v2f32(<2 x i8> %v) nounwind readnone { 119 ; CHECK-LABEL: test_unsigned_v2i8_to_v2f32 120 ; CHECK: movi d[[MASK:[0-9]+]], #0x0000ff000000ff 121 ; CHECK: and.8b [[VAL32:v[0-9]+]], v0, v[[MASK]] 122 ; CHECK: ucvtf.2s v0, [[VAL32]] 123 124 %conv = uitofp <2 x i8> %v to <2 x float> 125 ret <2 x float> %conv 126 } 127 128 define <4 x float> @test_signed_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone { 129 ; CHECK-LABEL: test_signed_v4i16_to_v4f32: 130 ; CHECK: sshll.4s [[VAL32:v[0-9]+]], v0, #0 131 ; CHECK: scvtf.4s v0, [[VAL32]] 132 133 %conv = sitofp <4 x i16> %v to <4 x float> 134 ret <4 x float> %conv 135 } 136 137 define <4 x float> @test_unsigned_v4i16_to_v4f32(<4 x i16> %v) nounwind readnone { 138 ; CHECK-LABEL: test_unsigned_v4i16_to_v4f32 139 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0 140 ; CHECK: ucvtf.4s v0, [[VAL32]] 141 142 %conv = uitofp <4 x i16> %v to <4 x float> 143 ret <4 x float> %conv 144 } 145 146 define <4 x float> @test_signed_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone { 147 ; CHECK-LABEL: test_signed_v4i8_to_v4f32: 148 ; CHECK: shl.4h [[TMP:v[0-9]+]], v0, #8 149 ; CHECK: sshr.4h [[VAL16:v[0-9]+]], [[TMP]], #8 150 ; CHECK: sshll.4s [[VAL32:v[0-9]+]], [[VAL16]], #0 151 ; CHECK: scvtf.4s v0, [[VAL32]] 152 153 %conv = sitofp <4 x i8> %v to <4 x float> 154 ret <4 x float> %conv 155 } 156 define <4 x float> @test_unsigned_v4i8_to_v4f32(<4 x i8> %v) nounwind readnone { 157 ; CHECK-LABEL: test_unsigned_v4i8_to_v4f32 158 ; CHECK: bic.4h v0, #0xff, lsl #8 159 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0 160 ; CHECK: ucvtf.4s v0, [[VAL32]] 161 162 %conv = uitofp <4 x i8> %v to <4 x float> 163 ret <4 x float> %conv 164 } 165
