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  /prebuilts/ndk/9/platforms/android-9/arch-x86/usr/include/asm/
io_32.h 31 #define BUILDIO(bwl,bw,type) static inline void out##bwl##_local(unsigned type value, int port) { __asm__ __volatile__("out" #bwl " %" #bw "0, %w1" : : "a"(value), "Nd"(port)); } static inline unsigned type in##bwl##_local(int port) { unsigned type value; __asm__ __volatile__("in" #bwl " %w1, %" #bw "0" : "=a"(value) : "Nd"(port)); return value; } static inline void out##bwl##_local_p(unsigned type value, int port) { out##bwl##_local(value, port); slow_down_io(); } static inline unsigned type in##bwl##_local_p(int port) { unsigned type value = in##bwl##_local(port); slow_down_io(); return value; } __BUILDIO(bwl,bw,type) static inline void out##bwl##_p(unsigned type value, int port) { out##bwl(value, port); slow_down_io(); } static inline unsigned type in##bwl##_p(int port) { unsigned type value = in##bwl(port); slow_down_io(); return value; } static inline void outs##bwl(int port, const void *addr, unsigned long count) { __asm__ __volatile__("rep; outs" #bwl : "+S"(addr), "+c"(count) : "d"(port)); } static inline void ins##bwl(int port, void *addr, unsigned long count) { __asm__ __volatile__("rep; ins" #bwl : "+D"(addr), "+c"(count) : "d"(port)); }
  /external/llvm/lib/Target/R600/
EvergreenInstructions.td 35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins,
40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins,
109 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
110 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> {
127 (outs R600_TReg32_X:$dst_gpr), pattern> {
139 (outs R600_TReg32_X:$dst_gpr), pattern> {
151 (outs R600_TReg32_X:$dst_gpr), pattern> {
172 (outs R600_Reg64:$dst_gpr), pattern> {
184 (outs R600_Reg128:$dst_gpr), pattern> {
351 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local), (int_AMDGPU_barrier_global)], AnyALU>
    [all...]
CaymanInstructions.td 83 class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
84 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> {
105 (outs R600_TReg32_X:$dst_gpr), pattern> {
116 (outs R600_TReg32_X:$dst_gpr), pattern> {
127 (outs R600_TReg32_X:$dst_gpr), pattern> {
147 (outs R600_Reg64:$dst_gpr), pattern> {
158 (outs R600_Reg128:$dst_gpr), pattern> {
R600Instructions.td 18 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
19 InstR600 <outs, ins, asm, pattern, NullALU> {
95 InstR600 <(outs R600_Reg32:$dst),
136 InstR600 <(outs R600_Reg32:$dst),
176 InstR600 <(outs R600_Reg32:$dst),
206 InstR600 <(outs R600_Reg32:$dst),
259 dag outs, dag ins, string asm, list<dag> pattern> :
260 InstR600ISA <outs, ins, asm, pattern>,
285 class VTX_READ <string name, bits<8> buffer_id, dag outs, list<dag> pattern>
286 : InstR600ISA <outs, (ins MEMxi:$src_gpr), name, pattern>
    [all...]
  /external/llvm/lib/Support/
CommandLine.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonInstrInfoV4.td 16 EXTENDERInst<(outs), ins, "immext(#$imm)", []>,
101 def TFR_FI_immext_V4 : ALU32_ri<(outs IntRegs:$dst),
110 def V4_A4_rcmpeqi : ALU32_ri<(outs IntRegs:$Rd),
128 def V4_A4_rcmpneqi : ALU32_ri<(outs IntRegs:$Rd),
138 def V4_A4_rcmpeq : ALU32_ri<(outs IntRegs:$Rd),
148 def V4_A4_rcmpneq : ALU32_ri<(outs IntRegs:$Rd),
169 def COMBINE_rI_V4 : ALU32_ri<(outs DoubleRegs:$dst),
178 def COMBINE_Ir_V4 : ALU32_ir<(outs DoubleRegs:$dst),
199 def COMBINE_iI_V4 : ALU32_ii<(outs DoubleRegs:$dst),
218 LDInst2<(outs RC:$dst1, IntRegs:$dst2)
    [all...]
  /external/llvm/lib/Target/ARM/
ARMInstrNEON.td 608 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
615 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
622 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
624 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
628 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
632 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
637 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
639 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
643 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
647 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb)
    [all...]
  /external/llvm/lib/Target/Mips/
MipsDSPInstrInfo.td 261 dag OutOperandList = (outs ROD:$rd);
271 dag OutOperandList = (outs ROD:$rd);
281 dag OutOperandList = (outs);
291 dag OutOperandList = (outs ROD:$rd);
301 dag OutOperandList = (outs ROT:$rt);
312 dag OutOperandList = (outs ROD:$rd);
321 dag OutOperandList = (outs RO:$rd);
330 dag OutOperandList = (outs RO:$rd);
340 dag OutOperandList = (outs RO:$rd);
350 dag OutOperandList = (outs GPR32Opnd:$rd)
    [all...]
Mips32r6InstrInfo.td 181 dag OutOperandList = (outs FGRCCOpnd:$fd);
247 dag OutOperandList = (outs GPROpnd:$rs);
259 dag OutOperandList = (outs GPROpnd:$rd);
268 dag OutOperandList = (outs GPROpnd:$rs);
278 dag OutOperandList = (outs GPROpnd:$rs);
294 dag OutOperandList = (outs);
302 dag OutOperandList = (outs);
310 dag OutOperandList = (outs);
318 dag OutOperandList = (outs);
354 dag OutOperandList = (outs);
    [all...]
MicroMipsInstrInfo.td 32 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
42 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
49 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
56 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
65 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
74 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
82 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
90 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
103 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
  /dalvik/dx/tests/054-dex-high16/
expected.txt 2 regs: 0002; ins: 0000; outs: 0002
15 regs: 0001; ins: 0000; outs: 0001
28 regs: 0001; ins: 0000; outs: 0001
49 regs: 0002; ins: 0000; outs: 0002
  /dalvik/dx/tests/056-dex-call-interface/
expected.txt 2 regs: 000b; ins: 0003; outs: 0003
  /dalvik/dx/tests/074-dex-form35c-edge-case/
expected.txt 2 regs: 0012; ins: 0001; outs: 0003
  /external/chromium_org/ppapi/native_client/src/trusted/plugin/
srpc_params.h 37 NaClSrpcArg** outs() const { return const_cast<NaClSrpcArg**>(outs_); } function in class:plugin::SrpcParams
  /external/llvm/examples/HowToUseJIT/
HowToUseJIT.cpp 119 outs() << "We just constructed this LLVM module:\n\n" << *M;
120 outs() << "\n\nRunning foo: ";
121 outs().flush();
128 outs() << "Result: " << gv.IntVal << "\n";
  /external/llvm/test/Transforms/CodeExtractor/
2004-03-14-DominanceProblem.ll 3 ; are dominated by all of the live-outs.
  /external/llvm/tools/llvm-jitlistener/
llvm-jitlistener.cpp 56 outs() << "Method load [" << msg->method_id << "]: " << msg->method_name
68 outs() << " Line info @ " << msg->line_number_table[i].Offset
72 outs() << "\n";
84 outs() << "Method unload [" << UnloadId << "]\n";
  /frameworks/rs/cpu_ref/linkloader/utils/
raw_ostream.cpp 25 static llvm::raw_ostream &singleton = llvm::outs();
  /frameworks/rs/cpu_ref/
rsCpuScriptGroup.h 45 Allocation *const* outs; member in struct:android::renderscript::CpuScriptGroupImpl::ScriptList
  /dalvik/dx/tests/080-dex-exception-tables/
expected.txt 2 regs: 0002; ins: 0000; outs: 0000
25 regs: 0002; ins: 0000; outs: 0000
52 regs: 0002; ins: 0000; outs: 0000
93 regs: 0002; ins: 0000; outs: 0000
130 regs: 0002; ins: 0000; outs: 0000
164 regs: 0002; ins: 0000; outs: 0000
199 regs: 0002; ins: 0000; outs: 0000
222 regs: 0002; ins: 0000; outs: 0000
247 regs: 0002; ins: 0000; outs: 0000
  /external/llvm/lib/Target/AArch64/
AArch64InstrFormats.td 787 : BaseSystemI<L, (outs), iops, asm, operands> {
852 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
862 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
906 : RtSystemI<L, (outs),
921 : RtSystemI<L, (outs),
956 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
963 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
1001 class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
1021 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
    [all...]
  /external/llvm/docs/
HowToUseInstrMappings.rst 121 def ADD : ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
126 def ADD_Pt : ALU32_rr<(outs IntRegs:$dst),
131 def ADD_Pf : ALU32_rr<(outs IntRegs:$dst),
142 def ADD : PredRel, ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$a, IntRegs:$b),
150 def ADD_Pt : PredRel, ALU32_rr<(outs IntRegs:$dst),
158 def ADD_Pf : PredRel, ALU32_rr<(outs IntRegs:$dst),
  /dalvik/dx/tests/052-dex-static-var-access/
expected.txt 2 regs: 0004; ins: 0000; outs: 0000
31 regs: 0008; ins: 0003; outs: 0000
  /external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
R600Instructions.td 16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
28 let OutOperandList = outs;
43 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
44 AMDGPUInst <outs, ins, asm, pattern>
81 (outs R600_Reg32:$dst),
91 (outs R600_Reg32:$dst),
101 (outs R600_Reg32:$dst),
112 def PRED_X : InstR600 <0, (outs R600_Predicate_Bit:$dst),
127 (outs),
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
R600Instructions.td 16 class InstR600 <bits<32> inst, dag outs, dag ins, string asm, list<dag> pattern,
18 : AMDGPUInst <outs, ins, asm, pattern> {
28 let OutOperandList = outs;
43 class InstR600ISA <dag outs, dag ins, string asm, list<dag> pattern> :
44 AMDGPUInst <outs, ins, asm, pattern>
81 (outs R600_Reg32:$dst),
91 (outs R600_Reg32:$dst),
101 (outs R600_Reg32:$dst),
112 def PRED_X : InstR600 <0, (outs R600_Predicate_Bit:$dst),
127 (outs),
    [all...]

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