1 //===-- EvergreenInstructions.td - EG Instruction defs ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // TableGen definitions for instructions which are: 11 // - Available to Evergreen and newer VLIW4/VLIW5 GPUs 12 // - Available only on Evergreen family GPUs. 13 // 14 //===----------------------------------------------------------------------===// 15 16 def isEG : Predicate< 17 "Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && " 18 "Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && " 19 "!Subtarget.hasCaymanISA()" 20 >; 21 22 def isEGorCayman : Predicate< 23 "Subtarget.getGeneration() == AMDGPUSubtarget::EVERGREEN ||" 24 "Subtarget.getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS" 25 >; 26 27 //===----------------------------------------------------------------------===// 28 // Evergreen / Cayman store instructions 29 //===----------------------------------------------------------------------===// 30 31 let Predicates = [isEGorCayman] in { 32 33 class CF_MEM_RAT_CACHELESS <bits<6> rat_inst, bits<4> rat_id, bits<4> mask, dag ins, 34 string name, list<dag> pattern> 35 : EG_CF_RAT <0x57, rat_inst, rat_id, mask, (outs), ins, 36 "MEM_RAT_CACHELESS "#name, pattern>; 37 38 class CF_MEM_RAT <bits<6> rat_inst, bits<4> rat_id, dag ins, string name, 39 list<dag> pattern> 40 : EG_CF_RAT <0x56, rat_inst, rat_id, 0xf /* mask */, (outs), ins, 41 "MEM_RAT "#name, pattern>; 42 43 def RAT_MSKOR : CF_MEM_RAT <0x11, 0, 44 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr), 45 "MSKOR $rw_gpr.XW, $index_gpr", 46 [(mskor_global v4i32:$rw_gpr, i32:$index_gpr)] 47 > { 48 let eop = 0; 49 } 50 51 } // End let Predicates = [isEGorCayman] 52 53 //===----------------------------------------------------------------------===// 54 // Evergreen Only instructions 55 //===----------------------------------------------------------------------===// 56 57 let Predicates = [isEG] in { 58 59 def RECIP_IEEE_eg : RECIP_IEEE_Common<0x86>; 60 defm DIV_eg : DIV_Common<RECIP_IEEE_eg>; 61 62 def MULLO_INT_eg : MULLO_INT_Common<0x8F>; 63 def MULHI_INT_eg : MULHI_INT_Common<0x90>; 64 def MULLO_UINT_eg : MULLO_UINT_Common<0x91>; 65 def MULHI_UINT_eg : MULHI_UINT_Common<0x92>; 66 def RECIP_UINT_eg : RECIP_UINT_Common<0x94>; 67 def RECIPSQRT_CLAMPED_eg : RECIPSQRT_CLAMPED_Common<0x87>; 68 def EXP_IEEE_eg : EXP_IEEE_Common<0x81>; 69 def LOG_IEEE_eg : LOG_IEEE_Common<0x83>; 70 def RECIP_CLAMPED_eg : RECIP_CLAMPED_Common<0x84>; 71 def RECIPSQRT_IEEE_eg : RECIPSQRT_IEEE_Common<0x89>; 72 def SIN_eg : SIN_Common<0x8D>; 73 def COS_eg : COS_Common<0x8E>; 74 75 def : POW_Common <LOG_IEEE_eg, EXP_IEEE_eg, MUL>; 76 def : Pat<(fsqrt f32:$src), (MUL $src, (RECIPSQRT_CLAMPED_eg $src))>; 77 78 defm : Expand24IBitOps<MULLO_INT_eg, ADD_INT>; 79 80 //===----------------------------------------------------------------------===// 81 // Memory read/write instructions 82 //===----------------------------------------------------------------------===// 83 84 let usesCustomInserter = 1 in { 85 86 // 32-bit store 87 def RAT_WRITE_CACHELESS_32_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x1, 88 (ins R600_TReg32_X:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 89 "STORE_RAW $rw_gpr, $index_gpr, $eop", 90 [(global_store i32:$rw_gpr, i32:$index_gpr)] 91 >; 92 93 // 64-bit store 94 def RAT_WRITE_CACHELESS_64_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0x3, 95 (ins R600_Reg64:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 96 "STORE_RAW $rw_gpr.XY, $index_gpr, $eop", 97 [(global_store v2i32:$rw_gpr, i32:$index_gpr)] 98 >; 99 100 //128-bit store 101 def RAT_WRITE_CACHELESS_128_eg : CF_MEM_RAT_CACHELESS <0x2, 0, 0xf, 102 (ins R600_Reg128:$rw_gpr, R600_TReg32_X:$index_gpr, InstFlag:$eop), 103 "STORE_RAW $rw_gpr.XYZW, $index_gpr, $eop", 104 [(global_store v4i32:$rw_gpr, i32:$index_gpr)] 105 >; 106 107 } // End usesCustomInserter = 1 108 109 class VTX_READ_eg <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 110 : VTX_WORD0_eg, VTX_READ<name, buffer_id, outs, pattern> { 111 112 // Static fields 113 let VC_INST = 0; 114 let FETCH_TYPE = 2; 115 let FETCH_WHOLE_QUAD = 0; 116 let BUFFER_ID = buffer_id; 117 let SRC_REL = 0; 118 // XXX: We can infer this field based on the SRC_GPR. This would allow us 119 // to store vertex addresses in any channel, not just X. 120 let SRC_SEL_X = 0; 121 122 let Inst{31-0} = Word0; 123 } 124 125 class VTX_READ_8_eg <bits<8> buffer_id, list<dag> pattern> 126 : VTX_READ_eg <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 127 (outs R600_TReg32_X:$dst_gpr), pattern> { 128 129 let MEGA_FETCH_COUNT = 1; 130 let DST_SEL_X = 0; 131 let DST_SEL_Y = 7; // Masked 132 let DST_SEL_Z = 7; // Masked 133 let DST_SEL_W = 7; // Masked 134 let DATA_FORMAT = 1; // FMT_8 135 } 136 137 class VTX_READ_16_eg <bits<8> buffer_id, list<dag> pattern> 138 : VTX_READ_eg <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 139 (outs R600_TReg32_X:$dst_gpr), pattern> { 140 let MEGA_FETCH_COUNT = 2; 141 let DST_SEL_X = 0; 142 let DST_SEL_Y = 7; // Masked 143 let DST_SEL_Z = 7; // Masked 144 let DST_SEL_W = 7; // Masked 145 let DATA_FORMAT = 5; // FMT_16 146 147 } 148 149 class VTX_READ_32_eg <bits<8> buffer_id, list<dag> pattern> 150 : VTX_READ_eg <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 151 (outs R600_TReg32_X:$dst_gpr), pattern> { 152 153 let MEGA_FETCH_COUNT = 4; 154 let DST_SEL_X = 0; 155 let DST_SEL_Y = 7; // Masked 156 let DST_SEL_Z = 7; // Masked 157 let DST_SEL_W = 7; // Masked 158 let DATA_FORMAT = 0xD; // COLOR_32 159 160 // This is not really necessary, but there were some GPU hangs that appeared 161 // to be caused by ALU instructions in the next instruction group that wrote 162 // to the $src_gpr registers of the VTX_READ. 163 // e.g. 164 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 165 // %T2_X<def> = MOV %ZERO 166 //Adding this constraint prevents this from happening. 167 let Constraints = "$src_gpr.ptr = $dst_gpr"; 168 } 169 170 class VTX_READ_64_eg <bits<8> buffer_id, list<dag> pattern> 171 : VTX_READ_eg <"VTX_READ_64 $dst_gpr.XY, $src_gpr", buffer_id, 172 (outs R600_Reg64:$dst_gpr), pattern> { 173 174 let MEGA_FETCH_COUNT = 8; 175 let DST_SEL_X = 0; 176 let DST_SEL_Y = 1; 177 let DST_SEL_Z = 7; 178 let DST_SEL_W = 7; 179 let DATA_FORMAT = 0x1D; // COLOR_32_32 180 } 181 182 class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> 183 : VTX_READ_eg <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 184 (outs R600_Reg128:$dst_gpr), pattern> { 185 186 let MEGA_FETCH_COUNT = 16; 187 let DST_SEL_X = 0; 188 let DST_SEL_Y = 1; 189 let DST_SEL_Z = 2; 190 let DST_SEL_W = 3; 191 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 192 193 // XXX: Need to force VTX_READ_128 instructions to write to the same register 194 // that holds its buffer address to avoid potential hangs. We can't use 195 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 196 // registers are different sizes. 197 } 198 199 //===----------------------------------------------------------------------===// 200 // VTX Read from parameter memory space 201 //===----------------------------------------------------------------------===// 202 203 def VTX_READ_PARAM_8_eg : VTX_READ_8_eg <0, 204 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 205 >; 206 207 def VTX_READ_PARAM_16_eg : VTX_READ_16_eg <0, 208 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 209 >; 210 211 def VTX_READ_PARAM_32_eg : VTX_READ_32_eg <0, 212 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 213 >; 214 215 def VTX_READ_PARAM_64_eg : VTX_READ_64_eg <0, 216 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 217 >; 218 219 def VTX_READ_PARAM_128_eg : VTX_READ_128_eg <0, 220 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 221 >; 222 223 //===----------------------------------------------------------------------===// 224 // VTX Read from global memory space 225 //===----------------------------------------------------------------------===// 226 227 // 8-bit reads 228 def VTX_READ_GLOBAL_8_eg : VTX_READ_8_eg <1, 229 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] 230 >; 231 232 def VTX_READ_GLOBAL_16_eg : VTX_READ_16_eg <1, 233 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] 234 >; 235 236 // 32-bit reads 237 def VTX_READ_GLOBAL_32_eg : VTX_READ_32_eg <1, 238 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 239 >; 240 241 // 64-bit reads 242 def VTX_READ_GLOBAL_64_eg : VTX_READ_64_eg <1, 243 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 244 >; 245 246 // 128-bit reads 247 def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1, 248 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 249 >; 250 251 } // End Predicates = [isEG] 252 253 //===----------------------------------------------------------------------===// 254 // Evergreen / Cayman Instructions 255 //===----------------------------------------------------------------------===// 256 257 let Predicates = [isEGorCayman] in { 258 259 // BFE_UINT - bit_extract, an optimization for mask and shift 260 // Src0 = Input 261 // Src1 = Offset 262 // Src2 = Width 263 // 264 // bit_extract = (Input << (32 - Offset - Width)) >> (32 - Width) 265 // 266 // Example Usage: 267 // (Offset, Width) 268 // 269 // (0, 8) = (Input << 24) >> 24 = (Input & 0xff) >> 0 270 // (8, 8) = (Input << 16) >> 24 = (Input & 0xffff) >> 8 271 // (16, 8) = (Input << 8) >> 24 = (Input & 0xffffff) >> 16 272 // (24, 8) = (Input << 0) >> 24 = (Input & 0xffffffff) >> 24 273 def BFE_UINT_eg : R600_3OP <0x4, "BFE_UINT", 274 [(set i32:$dst, (AMDGPUbfe_u32 i32:$src0, i32:$src1, i32:$src2))], 275 VecALU 276 >; 277 278 def BFE_INT_eg : R600_3OP <0x5, "BFE_INT", 279 [(set i32:$dst, (AMDGPUbfe_i32 i32:$src0, i32:$src1, i32:$src2))], 280 VecALU 281 >; 282 283 // XXX: This pattern is broken, disabling for now. See comment in 284 // AMDGPUInstructions.td for more info. 285 // def : BFEPattern <BFE_UINT_eg>; 286 def BFI_INT_eg : R600_3OP <0x06, "BFI_INT", 287 [(set i32:$dst, (AMDGPUbfi i32:$src0, i32:$src1, i32:$src2))], 288 VecALU 289 >; 290 291 def : Pat<(i32 (sext_inreg i32:$src, i1)), 292 (BFE_INT_eg i32:$src, (i32 ZERO), (i32 ONE_INT))>; 293 def : Pat<(i32 (sext_inreg i32:$src, i8)), 294 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 8))>; 295 def : Pat<(i32 (sext_inreg i32:$src, i16)), 296 (BFE_INT_eg i32:$src, (i32 ZERO), (MOV_IMM_I32 16))>; 297 298 defm : BFIPatterns <BFI_INT_eg, MOV_IMM_I32>; 299 300 def BFM_INT_eg : R600_2OP <0xA0, "BFM_INT", 301 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))], 302 VecALU 303 >; 304 305 def MULADD_UINT24_eg : R600_3OP <0x10, "MULADD_UINT24", 306 [(set i32:$dst, (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2))], VecALU 307 >; 308 309 def : UMad24Pat<MULADD_UINT24_eg>; 310 311 def BIT_ALIGN_INT_eg : R600_3OP <0xC, "BIT_ALIGN_INT", [], VecALU>; 312 def : ROTRPattern <BIT_ALIGN_INT_eg>; 313 def MULADD_eg : MULADD_Common<0x14>; 314 def MULADD_IEEE_eg : MULADD_IEEE_Common<0x18>; 315 def ASHR_eg : ASHR_Common<0x15>; 316 def LSHR_eg : LSHR_Common<0x16>; 317 def LSHL_eg : LSHL_Common<0x17>; 318 def CNDE_eg : CNDE_Common<0x19>; 319 def CNDGT_eg : CNDGT_Common<0x1A>; 320 def CNDGE_eg : CNDGE_Common<0x1B>; 321 def MUL_LIT_eg : MUL_LIT_Common<0x1F>; 322 def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>; 323 def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24", 324 [(set i32:$dst, (AMDGPUmul_u24 i32:$src0, i32:$src1))], VecALU 325 >; 326 def DOT4_eg : DOT4_Common<0xBE>; 327 defm CUBE_eg : CUBE_Common<0xC0>; 328 329 def BCNT_INT : R600_1OP_Helper <0xAA, "BCNT_INT", ctpop, VecALU>; 330 331 let hasSideEffects = 1 in { 332 def MOVA_INT_eg : R600_1OP <0xCC, "MOVA_INT", [], VecALU>; 333 } 334 335 def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common<MUL_LIT_eg, LOG_CLAMPED_eg, EXP_IEEE_eg>; 336 337 def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> { 338 let Pattern = []; 339 let Itinerary = AnyALU; 340 } 341 342 def INT_TO_FLT_eg : INT_TO_FLT_Common<0x9B>; 343 344 def FLT_TO_UINT_eg : FLT_TO_UINT_Common<0x9A> { 345 let Pattern = []; 346 } 347 348 def UINT_TO_FLT_eg : UINT_TO_FLT_Common<0x9C>; 349 350 def GROUP_BARRIER : InstR600 < 351 (outs), (ins), " GROUP_BARRIER", [(int_AMDGPU_barrier_local), (int_AMDGPU_barrier_global)], AnyALU>, 352 R600ALU_Word0, 353 R600ALU_Word1_OP2 <0x54> { 354 355 let dst = 0; 356 let dst_rel = 0; 357 let src0 = 0; 358 let src0_rel = 0; 359 let src0_neg = 0; 360 let src0_abs = 0; 361 let src1 = 0; 362 let src1_rel = 0; 363 let src1_neg = 0; 364 let src1_abs = 0; 365 let write = 0; 366 let omod = 0; 367 let clamp = 0; 368 let last = 1; 369 let bank_swizzle = 0; 370 let pred_sel = 0; 371 let update_exec_mask = 0; 372 let update_pred = 0; 373 374 let Inst{31-0} = Word0; 375 let Inst{63-32} = Word1; 376 377 let ALUInst = 1; 378 } 379 380 def : Pat < 381 (int_AMDGPU_barrier_global), 382 (GROUP_BARRIER) 383 >; 384 385 //===----------------------------------------------------------------------===// 386 // LDS Instructions 387 //===----------------------------------------------------------------------===// 388 class R600_LDS <bits<6> op, dag outs, dag ins, string asm, 389 list<dag> pattern = []> : 390 391 InstR600 <outs, ins, asm, pattern, XALU>, 392 R600_ALU_LDS_Word0, 393 R600LDS_Word1 { 394 395 bits<6> offset = 0; 396 let lds_op = op; 397 398 let Word1{27} = offset{0}; 399 let Word1{12} = offset{1}; 400 let Word1{28} = offset{2}; 401 let Word1{31} = offset{3}; 402 let Word0{12} = offset{4}; 403 let Word0{25} = offset{5}; 404 405 406 let Inst{31-0} = Word0; 407 let Inst{63-32} = Word1; 408 409 let ALUInst = 1; 410 let HasNativeOperands = 1; 411 let UseNamedOperandTable = 1; 412 } 413 414 class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS < 415 lds_op, 416 (outs R600_Reg32:$dst), 417 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 418 LAST:$last, R600_Pred:$pred_sel, 419 BANK_SWIZZLE:$bank_swizzle), 420 " "#name#" $last OQAP, $src0$src0_rel $pred_sel", 421 pattern 422 > { 423 424 let src1 = 0; 425 let src1_rel = 0; 426 let src2 = 0; 427 let src2_rel = 0; 428 429 let usesCustomInserter = 1; 430 let LDS_1A = 1; 431 let DisableEncoding = "$dst"; 432 } 433 434 class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern, 435 string dst =""> : 436 R600_LDS < 437 lds_op, outs, 438 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 439 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 440 LAST:$last, R600_Pred:$pred_sel, 441 BANK_SWIZZLE:$bank_swizzle), 442 " "#name#" $last "#dst#"$src0$src0_rel, $src1$src1_rel, $pred_sel", 443 pattern 444 > { 445 446 field string BaseOp; 447 448 let src2 = 0; 449 let src2_rel = 0; 450 let LDS_1A1D = 1; 451 } 452 453 class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> : 454 R600_LDS_1A1D <lds_op, (outs), name, pattern> { 455 let BaseOp = name; 456 } 457 458 class R600_LDS_1A1D_RET <bits<6> lds_op, string name, list<dag> pattern> : 459 R600_LDS_1A1D <lds_op, (outs R600_Reg32:$dst), name##"_RET", pattern, "OQAP, "> { 460 461 let BaseOp = name; 462 let usesCustomInserter = 1; 463 let DisableEncoding = "$dst"; 464 } 465 466 class R600_LDS_1A2D <bits<6> lds_op, string name, list<dag> pattern> : 467 R600_LDS < 468 lds_op, 469 (outs), 470 (ins R600_Reg32:$src0, REL:$src0_rel, SEL:$src0_sel, 471 R600_Reg32:$src1, REL:$src1_rel, SEL:$src1_sel, 472 R600_Reg32:$src2, REL:$src2_rel, SEL:$src2_sel, 473 LAST:$last, R600_Pred:$pred_sel, BANK_SWIZZLE:$bank_swizzle), 474 " "#name# "$last $src0$src0_rel, $src1$src1_rel, $src2$src2_rel, $pred_sel", 475 pattern> { 476 let LDS_1A2D = 1; 477 } 478 479 def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >; 480 def LDS_SUB : R600_LDS_1A1D_NORET <0x1, "LDS_SUB", [] >; 481 def LDS_WRITE : R600_LDS_1A1D_NORET <0xD, "LDS_WRITE", 482 [(local_store (i32 R600_Reg32:$src1), R600_Reg32:$src0)] 483 >; 484 def LDS_BYTE_WRITE : R600_LDS_1A1D_NORET<0x12, "LDS_BYTE_WRITE", 485 [(truncstorei8_local i32:$src1, i32:$src0)] 486 >; 487 def LDS_SHORT_WRITE : R600_LDS_1A1D_NORET<0x13, "LDS_SHORT_WRITE", 488 [(truncstorei16_local i32:$src1, i32:$src0)] 489 >; 490 def LDS_ADD_RET : R600_LDS_1A1D_RET <0x20, "LDS_ADD", 491 [(set i32:$dst, (atomic_load_add_local i32:$src0, i32:$src1))] 492 >; 493 def LDS_SUB_RET : R600_LDS_1A1D_RET <0x21, "LDS_SUB", 494 [(set i32:$dst, (atomic_load_sub_local i32:$src0, i32:$src1))] 495 >; 496 def LDS_READ_RET : R600_LDS_1A <0x32, "LDS_READ_RET", 497 [(set (i32 R600_Reg32:$dst), (local_load R600_Reg32:$src0))] 498 >; 499 def LDS_BYTE_READ_RET : R600_LDS_1A <0x36, "LDS_BYTE_READ_RET", 500 [(set i32:$dst, (sextloadi8_local i32:$src0))] 501 >; 502 def LDS_UBYTE_READ_RET : R600_LDS_1A <0x37, "LDS_UBYTE_READ_RET", 503 [(set i32:$dst, (az_extloadi8_local i32:$src0))] 504 >; 505 def LDS_SHORT_READ_RET : R600_LDS_1A <0x38, "LDS_SHORT_READ_RET", 506 [(set i32:$dst, (sextloadi16_local i32:$src0))] 507 >; 508 def LDS_USHORT_READ_RET : R600_LDS_1A <0x39, "LDS_USHORT_READ_RET", 509 [(set i32:$dst, (az_extloadi16_local i32:$src0))] 510 >; 511 512 // TRUNC is used for the FLT_TO_INT instructions to work around a 513 // perceived problem where the rounding modes are applied differently 514 // depending on the instruction and the slot they are in. 515 // See: 516 // https://bugs.freedesktop.org/show_bug.cgi?id=50232 517 // Mesa commit: a1a0974401c467cb86ef818f22df67c21774a38c 518 // 519 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes, 520 // which do not need to be truncated since the fp values are 0.0f or 1.0f. 521 // We should look into handling these cases separately. 522 def : Pat<(fp_to_sint f32:$src0), (FLT_TO_INT_eg (TRUNC $src0))>; 523 524 def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>; 525 526 // SHA-256 Patterns 527 def : SHA256MaPattern <BFI_INT_eg, XOR_INT>; 528 529 def : FROUNDPat <CNDGE_eg>; 530 531 def EG_ExportSwz : ExportSwzInst { 532 let Word1{19-16} = 0; // BURST_COUNT 533 let Word1{20} = 0; // VALID_PIXEL_MODE 534 let Word1{21} = eop; 535 let Word1{29-22} = inst; 536 let Word1{30} = 0; // MARK 537 let Word1{31} = 1; // BARRIER 538 } 539 defm : ExportPattern<EG_ExportSwz, 83>; 540 541 def EG_ExportBuf : ExportBufInst { 542 let Word1{19-16} = 0; // BURST_COUNT 543 let Word1{20} = 0; // VALID_PIXEL_MODE 544 let Word1{21} = eop; 545 let Word1{29-22} = inst; 546 let Word1{30} = 0; // MARK 547 let Word1{31} = 1; // BARRIER 548 } 549 defm : SteamOutputExportPattern<EG_ExportBuf, 0x40, 0x41, 0x42, 0x43>; 550 551 def CF_TC_EG : CF_CLAUSE_EG<1, (ins i32imm:$ADDR, i32imm:$COUNT), 552 "TEX $COUNT @$ADDR"> { 553 let POP_COUNT = 0; 554 } 555 def CF_VC_EG : CF_CLAUSE_EG<2, (ins i32imm:$ADDR, i32imm:$COUNT), 556 "VTX $COUNT @$ADDR"> { 557 let POP_COUNT = 0; 558 } 559 def WHILE_LOOP_EG : CF_CLAUSE_EG<6, (ins i32imm:$ADDR), 560 "LOOP_START_DX10 @$ADDR"> { 561 let POP_COUNT = 0; 562 let COUNT = 0; 563 } 564 def END_LOOP_EG : CF_CLAUSE_EG<5, (ins i32imm:$ADDR), "END_LOOP @$ADDR"> { 565 let POP_COUNT = 0; 566 let COUNT = 0; 567 } 568 def LOOP_BREAK_EG : CF_CLAUSE_EG<9, (ins i32imm:$ADDR), 569 "LOOP_BREAK @$ADDR"> { 570 let POP_COUNT = 0; 571 let COUNT = 0; 572 } 573 def CF_CONTINUE_EG : CF_CLAUSE_EG<8, (ins i32imm:$ADDR), 574 "CONTINUE @$ADDR"> { 575 let POP_COUNT = 0; 576 let COUNT = 0; 577 } 578 def CF_JUMP_EG : CF_CLAUSE_EG<10, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 579 "JUMP @$ADDR POP:$POP_COUNT"> { 580 let COUNT = 0; 581 } 582 def CF_PUSH_EG : CF_CLAUSE_EG<11, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 583 "PUSH @$ADDR POP:$POP_COUNT"> { 584 let COUNT = 0; 585 } 586 def CF_ELSE_EG : CF_CLAUSE_EG<13, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 587 "ELSE @$ADDR POP:$POP_COUNT"> { 588 let COUNT = 0; 589 } 590 def CF_CALL_FS_EG : CF_CLAUSE_EG<19, (ins), "CALL_FS"> { 591 let ADDR = 0; 592 let COUNT = 0; 593 let POP_COUNT = 0; 594 } 595 def POP_EG : CF_CLAUSE_EG<14, (ins i32imm:$ADDR, i32imm:$POP_COUNT), 596 "POP @$ADDR POP:$POP_COUNT"> { 597 let COUNT = 0; 598 } 599 def CF_END_EG : CF_CLAUSE_EG<0, (ins), "CF_END"> { 600 let COUNT = 0; 601 let POP_COUNT = 0; 602 let ADDR = 0; 603 let END_OF_PROGRAM = 1; 604 } 605 606 } // End Predicates = [isEGorCayman] 607
