| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | [all...] |
| AMDILCFGStructurizer.cpp | 508 MachineInstrBuilder MIB(*MF, NewMI);
509 MIB.addReg(OldMI->getOperand(1).getReg(), false);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 706 MachineInstrBuilder MIB =
710 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
713 MIB.addOperand(MI->getOperand(I));
714 return finishConvertToThreeAddress(MI, MIB, LV);
735 MachineInstrBuilder MIB =
740 return finishConvertToThreeAddress(MI, MIB, LV);
851 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
853 MIB.addOperand(MI->getOperand(I));
854 MIB.addFrameIndex(FrameIndex).addImm(Offset);
856 MIB.addReg(0)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 674 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
676 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
680 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
685 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
[all...] |
| ARMBaseRegisterInfo.cpp | 598 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
602 AddDefaultCC(MIB);
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86FastISel.cpp | 413 MachineInstrBuilder MIB =
415 addFullAddress(MIB, AM);
417 MIB->addMemOperand(*FuncInfo.MF, MMO);
477 MachineInstrBuilder MIB =
479 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill));
481 MIB->addMemOperand(*FuncInfo.MF, MMO);
511 MachineInstrBuilder MIB =
513 addFullAddress(MIB, AM).addImm(Signed ? (uint64_t) CI->getSExtValue()
516 MIB->addMemOperand(*FuncInfo.MF, MMO);
[all...] |
| X86FrameLowering.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 118 void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
495 const MachineInstrBuilder &MIB,
507 MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
510 MIB.addReg(Addr.getReg());
511 MIB.addImm(Offset);
579 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
581 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, UseUnscaled);
683 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
685 AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, UseUnscaled);
[all...] |
| AArch64ConditionalCompares.cpp | 656 MachineInstrBuilder MIB =
660 MIB.addImm(0); // cbz/cbnz Rn -> ccmp Rn, #0
662 MIB.addOperand(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate
663 MIB.addImm(NZCV).addImm(HeadCmpBBCC);
|
| AArch64FrameLowering.cpp | 678 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
680 MIB.addReg(AArch64::SP, RegState::Define);
682 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2))
748 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
750 MIB.addReg(AArch64::SP, RegState::Define);
752 MIB.addReg(Reg2, getDefRegState(true))
[all...] |
| AArch64InstrInfo.cpp | 263 const MachineInstrBuilder MIB =
266 MIB.addImm(Cond[3].getImm());
267 MIB.addMBB(TBB);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 409 MachineInstrBuilder MIB(MF, NewMI);
413 MIB.addOperand(MI->getOperand(i));
427 MIB.addImm(StackMaps::IndirectMemRefOp);
428 MIB.addImm(SpillSize);
429 MIB.addFrameIndex(FrameIndex);
430 MIB.addImm(SpillOffset);
433 MIB.addOperand(MO);
|
| TargetLoweringBase.cpp | [all...] |
| TailDuplication.cpp | 472 MachineInstrBuilder MIB(*FromBB->getParent(), II);
520 MIB.addReg(SrcReg).addMBB(SrcBB);
532 MIB.addReg(Reg).addMBB(SrcBB);
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelDAGToDAG.cpp | 47 MachineInstrBuilder MIB(MF, &MI);
52 MIB.addReg(Mips::DSPPos, Flag);
55 MIB.addReg(Mips::DSPSCount, Flag);
58 MIB.addReg(Mips::DSPCarry, Flag);
61 MIB.addReg(Mips::DSPOutFlag, Flag);
64 MIB.addReg(Mips::DSPCCond, Flag);
67 MIB.addReg(Mips::DSPEFI, Flag);
|
| MipsLongBranch.cpp | 224 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
234 MIB.addReg(MO.getReg());
237 MIB.addMBB(MBBOpnd);
243 MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
|
| MipsSEInstrInfo.cpp | 170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
173 MIB.addReg(DestReg, RegState::Define);
176 MIB.addReg(SrcReg, getKillRegState(KillSrc));
179 MIB.addReg(ZeroReg);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 182 MachineInstrBuilder MIB =
185 MIB->copyImplicitOps(*MBB.getParent(), &*MBBI);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 263 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
264 MIB.addImm(Adjusted);
265 MIB->addRegisterKilled(XCore::LR, MF.getTarget().getRegisterInfo(), true);
393 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
396 MIB->addOperand(MBBI->getOperand(i)); // copy any variadic operands
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
