| /external/llvm/lib/Target/R600/InstPrinter/ |
| AMDGPUInstPrinter.h | 42 static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
|
| AMDGPUInstPrinter.cpp | 173 void AMDGPUInstPrinter::printInterpSlot(const MCInst *MI, unsigned OpNum,
175 unsigned Imm = MI->getOperand(OpNum).getImm();
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 376 unsigned OpNum = 3; // First 'rest' of operands.
414 OpNum = 4;
435 OpNum = 0;
444 OpNum = 2;
452 OpNum = 0;
459 OpNum = 2;
509 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
510 MIB.addOperand(MI->getOperand(OpNum));
[all...] |
| ARMLoadStoreOptimizer.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 317 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
320 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
323 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
326 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExecutionDepsFix.cpp | 499 unsigned OpNum;
500 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
502 if (shouldBreakDependence(MI, OpNum, Pref))
503 UndefReads.push_back(std::make_pair(MI, OpNum));
|
| TargetInstrInfo.cpp | 42 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
45 if (OpNum >= MCID.getNumOperands())
48 short RegClass = MCID.OpInfo[OpNum].RegClass;
49 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 771 unsigned OpNum = Ops[0];
773 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
777 OpNum == 0 &&
791 if (OpNum == 0) {
799 if (OpNum == 1) {
820 if (OpNum == 0 && MI->hasOneMemOperand()) {
845 if (OpNum == NumOps - 1) {
852 for (unsigned I = 0; I < OpNum; ++I)
[all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| rpcasync.h | 289 unsigned short OpNum;
310 unsigned short OpNum;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64BranchRelaxation.cpp | 389 unsigned OpNum = (MI->getOpcode() == AArch64::TBZW ||
395 MI->getOperand(OpNum).setMBB(NewDest);
|
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 348 /// Try to constrain Op so that it is usable by argument OpNum of the provided
352 unsigned OpNum);
|
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 89 unsigned OpNum) const {
90 unsigned SrcReg = MI.getOperand(OpNum).getReg();
91 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
101 unsigned OpNum) const {
102 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
104 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
[all...] |
| /hardware/intel/img/psb_video/src/ |
| pnw_hostjpeg.h | 400 IMG_UINT32 OpNum;
|
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 115 unsigned OpNum) const;
712 unsigned OpNum) const {
713 unsigned SrcReg = MI.getOperand(OpNum).getReg();
714 unsigned SrcRegNum = getX86RegNum(MI.getOperand(OpNum).getReg());
[all...] |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | 706 unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
707 const MachineOperand &MO = MI->getOperand(OpNum);
[all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
