| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
270 unsigned RegNo = TRI->getEncodingValue(I->first);
286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
[all...] |
| PPCInstrInfo.cpp | 118 const TargetRegisterInfo *TRI = &getRegisterInfo();
120 if (TRI->isVirtualRegister(Reg)) {
695 const TargetRegisterInfo *TRI = &getRegisterInfo();
699 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
708 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
717 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
726 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
854 const TargetRegisterInfo *TRI) const {
[all...] |
| /external/llvm/lib/CodeGen/ |
| InlineSpiller.cpp | 70 const TargetRegisterInfo &TRI;
155 TRI(*mf.getTarget().getRegisterInfo()),
745 MRI.getRegClass(SVI.SpillReg), &TRI);
[all...] |
| SplitKit.h | 218 const TargetRegisterInfo &TRI;
|
| IfConversion.cpp | 163 const TargetRegisterInfo *TRI;
274 TRI = MF.getTarget().getRegisterInfo();
[all...] |
| MachineBasicBlock.cpp | 293 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
298 OS << ' ' << PrintReg(*I, TRI);
826 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
832 if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
[all...] |
| MachineFunction.cpp | 353 const TargetRegisterInfo *TRI = getTarget().getRegisterInfo();
359 OS << PrintReg(I->first, TRI);
361 OS << " in " << PrintReg(I->second, TRI);
603 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
604 BitVector BV(TRI->getNumRegs());
611 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR)
[all...] |
| MachineScheduler.cpp | 870 dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
894 DEBUG(dbgs() << TRI->getRegPressureSetName(i)
902 dbgs() << TRI->getRegPressureSetName(
[all...] |
| ScheduleDAG.cpp | 40 TRI(TM.getRegisterInfo()),
352 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
372 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
|
| MachineSink.cpp | 48 const TargetRegisterInfo *TRI;
218 TRI = TM.getRegisterInfo();
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| TailDuplication.cpp | 64 const TargetRegisterInfo *TRI;
139 TRI = MF.getTarget().getRegisterInfo();
146 if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
801 BitVector RegsLiveAtExit(TRI->getNumRegs());
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineTraceMetrics.h | 70 const TargetRegisterInfo *TRI;
|
| FastISel.h | 61 const TargetRegisterInfo &TRI;
|
| LiveIntervalAnalysis.h | 54 const TargetRegisterInfo* TRI;
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 92 const TargetRegisterInfo &TRI,
131 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
152 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) {
172 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);
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| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 183 const TargetRegisterInfo *TRI) const {
209 const TargetRegisterInfo *TRI) const {
|
| MSP430InstrInfo.cpp | 41 const TargetRegisterInfo *TRI) const {
69 const TargetRegisterInfo *TRI) const{
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 618 const TargetRegisterInfo *TRI) const {
670 DEBUG(dbgs() << "CSR spill: (" << TRI->getName(Reg1) << ", "
671 << TRI->getName(Reg2) << ") -> fi#(" << CSI[idx].getFrameIdx()
694 const TargetRegisterInfo *TRI) const {
739 DEBUG(dbgs() << "CSR restore: (" << TRI->getName(Reg1) << ", "
740 << TRI->getName(Reg2) << ") -> fi#(" << CSI[i].getFrameIdx()
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 411 const TargetRegisterInfo *TRI) const {
432 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
433 TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
447 const TargetRegisterInfo *TRI) const{
460 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
461 TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
|
| XCoreInstrInfo.cpp | 373 const TargetRegisterInfo *TRI) const
396 const TargetRegisterInfo *TRI) const
|
| /external/llvm/lib/Target/ARM/ |
| ARMLoadStoreOptimizer.cpp | 69 const TargetRegisterInfo *TRI;
721 unsigned PRegNum = PMO.isUndef() ? UINT_MAX : TRI->getEncodingValue(PReg);
747 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
[all...] |
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
228 const TargetRegisterInfo *TRI, int64_t Offset) const {
549 const TargetRegisterInfo &TRI = getRegisterInfo();
566 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
588 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
|
| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.cpp | 31 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
|
| SIISelLowering.cpp | 312 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
417 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
[all...] |
