1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI_EXYNOS_DRM_H_ 20 #define _UAPI_EXYNOS_DRM_H_ 21 #include <drm/drm.h> 22 struct drm_exynos_gem_create { 23 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 24 uint64_t size; 25 unsigned int flags; 26 unsigned int handle; 27 }; 28 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 29 struct drm_exynos_gem_map_off { 30 unsigned int handle; 31 unsigned int pad; 32 uint64_t offset; 33 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 34 }; 35 struct drm_exynos_gem_mmap { 36 unsigned int handle; 37 unsigned int pad; 38 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 39 uint64_t size; 40 uint64_t mapped; 41 }; 42 struct drm_exynos_gem_info { 43 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 44 unsigned int handle; 45 unsigned int flags; 46 uint64_t size; 47 }; 48 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 49 struct drm_exynos_vidi_connection { 50 unsigned int connection; 51 unsigned int extensions; 52 uint64_t edid; 53 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 54 }; 55 enum e_drm_exynos_gem_mem_type { 56 EXYNOS_BO_CONTIG = 0 << 0, 57 EXYNOS_BO_NONCONTIG = 1 << 0, 58 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 59 EXYNOS_BO_NONCACHABLE = 0 << 1, 60 EXYNOS_BO_CACHABLE = 1 << 1, 61 EXYNOS_BO_WC = 1 << 2, 62 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | 63 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 64 EXYNOS_BO_WC 65 }; 66 struct drm_exynos_g2d_get_ver { 67 __u32 major; 68 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 69 __u32 minor; 70 }; 71 struct drm_exynos_g2d_cmd { 72 __u32 offset; 73 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 74 __u32 data; 75 }; 76 enum drm_exynos_g2d_buf_type { 77 G2D_BUF_USERPTR = 1 << 31, 78 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 79 }; 80 enum drm_exynos_g2d_event_type { 81 G2D_EVENT_NOT, 82 G2D_EVENT_NONSTOP, 83 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 84 G2D_EVENT_STOP, 85 }; 86 struct drm_exynos_g2d_userptr { 87 unsigned long userptr; 88 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 89 unsigned long size; 90 }; 91 struct drm_exynos_g2d_set_cmdlist { 92 __u64 cmd; 93 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 94 __u64 cmd_buf; 95 __u32 cmd_nr; 96 __u32 cmd_buf_nr; 97 __u64 event_type; 98 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 99 __u64 user_data; 100 }; 101 struct drm_exynos_g2d_exec { 102 __u64 async; 103 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 104 }; 105 enum drm_exynos_ops_id { 106 EXYNOS_DRM_OPS_SRC, 107 EXYNOS_DRM_OPS_DST, 108 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 109 EXYNOS_DRM_OPS_MAX, 110 }; 111 struct drm_exynos_sz { 112 __u32 hsize; 113 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 114 __u32 vsize; 115 }; 116 struct drm_exynos_pos { 117 __u32 x; 118 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 119 __u32 y; 120 __u32 w; 121 __u32 h; 122 }; 123 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 124 enum drm_exynos_flip { 125 EXYNOS_DRM_FLIP_NONE = (0 << 0), 126 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 127 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 128 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 129 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | 130 EXYNOS_DRM_FLIP_HORIZONTAL, 131 }; 132 enum drm_exynos_degree { 133 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 134 EXYNOS_DRM_DEGREE_0, 135 EXYNOS_DRM_DEGREE_90, 136 EXYNOS_DRM_DEGREE_180, 137 EXYNOS_DRM_DEGREE_270, 138 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 139 }; 140 enum drm_exynos_planer { 141 EXYNOS_DRM_PLANAR_Y, 142 EXYNOS_DRM_PLANAR_CB, 143 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 144 EXYNOS_DRM_PLANAR_CR, 145 EXYNOS_DRM_PLANAR_MAX, 146 }; 147 struct drm_exynos_ipp_prop_list { 148 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 149 __u32 version; 150 __u32 ipp_id; 151 __u32 count; 152 __u32 writeback; 153 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 154 __u32 flip; 155 __u32 degree; 156 __u32 csc; 157 __u32 crop; 158 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 159 __u32 scale; 160 __u32 refresh_min; 161 __u32 refresh_max; 162 __u32 reserved; 163 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 164 struct drm_exynos_sz crop_min; 165 struct drm_exynos_sz crop_max; 166 struct drm_exynos_sz scale_min; 167 struct drm_exynos_sz scale_max; 168 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 169 }; 170 struct drm_exynos_ipp_config { 171 enum drm_exynos_ops_id ops_id; 172 enum drm_exynos_flip flip; 173 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 174 enum drm_exynos_degree degree; 175 __u32 fmt; 176 struct drm_exynos_sz sz; 177 struct drm_exynos_pos pos; 178 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 179 }; 180 enum drm_exynos_ipp_cmd { 181 IPP_CMD_NONE, 182 IPP_CMD_M2M, 183 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 184 IPP_CMD_WB, 185 IPP_CMD_OUTPUT, 186 IPP_CMD_MAX, 187 }; 188 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 189 struct drm_exynos_ipp_property { 190 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 191 enum drm_exynos_ipp_cmd cmd; 192 __u32 ipp_id; 193 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 194 __u32 prop_id; 195 __u32 refresh_rate; 196 }; 197 enum drm_exynos_ipp_buf_type { 198 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 199 IPP_BUF_ENQUEUE, 200 IPP_BUF_DEQUEUE, 201 }; 202 struct drm_exynos_ipp_queue_buf { 203 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 204 enum drm_exynos_ops_id ops_id; 205 enum drm_exynos_ipp_buf_type buf_type; 206 __u32 prop_id; 207 __u32 buf_id; 208 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 209 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 210 __u32 reserved; 211 __u64 user_data; 212 }; 213 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 214 enum drm_exynos_ipp_ctrl { 215 IPP_CTRL_PLAY, 216 IPP_CTRL_STOP, 217 IPP_CTRL_PAUSE, 218 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 219 IPP_CTRL_RESUME, 220 IPP_CTRL_MAX, 221 }; 222 struct drm_exynos_ipp_cmd_ctrl { 223 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 224 __u32 prop_id; 225 enum drm_exynos_ipp_ctrl ctrl; 226 }; 227 #define DRM_EXYNOS_GEM_CREATE 0x00 228 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 229 #define DRM_EXYNOS_GEM_MAP_OFFSET 0x01 230 #define DRM_EXYNOS_GEM_MMAP 0x02 231 #define DRM_EXYNOS_GEM_GET 0x04 232 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 233 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 234 #define DRM_EXYNOS_G2D_GET_VER 0x20 235 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 236 #define DRM_EXYNOS_G2D_EXEC 0x22 237 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 238 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 239 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 240 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 241 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 242 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 243 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 244 #define DRM_IOCTL_EXYNOS_GEM_MAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MAP_OFFSET, struct drm_exynos_gem_map_off) 245 #define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) 246 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 247 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 248 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 249 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 250 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 251 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 252 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 253 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 254 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 255 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 256 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 257 #define DRM_EXYNOS_G2D_EVENT 0x80000000 258 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 259 #define DRM_EXYNOS_IPP_EVENT 0x80000001 260 struct drm_exynos_g2d_event { 261 struct drm_event base; 262 __u64 user_data; 263 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 264 __u32 tv_sec; 265 __u32 tv_usec; 266 __u32 cmdlist_no; 267 __u32 reserved; 268 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 269 }; 270 struct drm_exynos_ipp_event { 271 struct drm_event base; 272 __u64 user_data; 273 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 274 __u32 tv_sec; 275 __u32 tv_usec; 276 __u32 prop_id; 277 __u32 reserved; 278 /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ 279 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 280 }; 281 #endif 282
