1 #!/usr/bin/env perl 2 # 3 # ==================================================================== 4 # Written by Andy Polyakov <appro (at] fy.chalmers.se> for the OpenSSL 5 # project. The module is, however, dual licensed under OpenSSL and 6 # CRYPTOGAMS licenses depending on where you obtain it. For further 7 # details see http://www.openssl.org/~appro/cryptogams/. 8 # ==================================================================== 9 # 10 # July 2004 11 # 12 # 2.22x RC4 tune-up:-) It should be noted though that my hand [as in 13 # "hand-coded assembler"] doesn't stand for the whole improvement 14 # coefficient. It turned out that eliminating RC4_CHAR from config 15 # line results in ~40% improvement (yes, even for C implementation). 16 # Presumably it has everything to do with AMD cache architecture and 17 # RAW or whatever penalties. Once again! The module *requires* config 18 # line *without* RC4_CHAR! As for coding "secret," I bet on partial 19 # register arithmetics. For example instead of 'inc %r8; and $255,%r8' 20 # I simply 'inc %r8b'. Even though optimization manual discourages 21 # to operate on partial registers, it turned out to be the best bet. 22 # At least for AMD... How IA32E would perform remains to be seen... 23 24 # November 2004 25 # 26 # As was shown by Marc Bevand reordering of couple of load operations 27 # results in even higher performance gain of 3.3x:-) At least on 28 # Opteron... For reference, 1x in this case is RC4_CHAR C-code 29 # compiled with gcc 3.3.2, which performs at ~54MBps per 1GHz clock. 30 # Latter means that if you want to *estimate* what to expect from 31 # *your* Opteron, then multiply 54 by 3.3 and clock frequency in GHz. 32 33 # November 2004 34 # 35 # Intel P4 EM64T core was found to run the AMD64 code really slow... 36 # The only way to achieve comparable performance on P4 was to keep 37 # RC4_CHAR. Kind of ironic, huh? As it's apparently impossible to 38 # compose blended code, which would perform even within 30% marginal 39 # on either AMD and Intel platforms, I implement both cases. See 40 # rc4_skey.c for further details... 41 42 # April 2005 43 # 44 # P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing 45 # those with add/sub results in 50% performance improvement of folded 46 # loop... 47 48 # May 2005 49 # 50 # As was shown by Zou Nanhai loop unrolling can improve Intel EM64T 51 # performance by >30% [unlike P4 32-bit case that is]. But this is 52 # provided that loads are reordered even more aggressively! Both code 53 # pathes, AMD64 and EM64T, reorder loads in essentially same manner 54 # as my IA-64 implementation. On Opteron this resulted in modest 5% 55 # improvement [I had to test it], while final Intel P4 performance 56 # achieves respectful 432MBps on 2.8GHz processor now. For reference. 57 # If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than 58 # RC4_INT code-path. While if executed on Opteron, it's only 25% 59 # slower than the RC4_INT one [meaning that if CPU -arch detection 60 # is not implemented, then this final RC4_CHAR code-path should be 61 # preferred, as it provides better *all-round* performance]. 62 63 # March 2007 64 # 65 # Intel Core2 was observed to perform poorly on both code paths:-( It 66 # apparently suffers from some kind of partial register stall, which 67 # occurs in 64-bit mode only [as virtually identical 32-bit loop was 68 # observed to outperform 64-bit one by almost 50%]. Adding two movzb to 69 # cloop1 boosts its performance by 80%! This loop appears to be optimal 70 # fit for Core2 and therefore the code was modified to skip cloop8 on 71 # this CPU. 72 73 # May 2010 74 # 75 # Intel Westmere was observed to perform suboptimally. Adding yet 76 # another movzb to cloop1 improved performance by almost 50%! Core2 77 # performance is improved too, but nominally... 78 79 # May 2011 80 # 81 # The only code path that was not modified is P4-specific one. Non-P4 82 # Intel code path optimization is heavily based on submission by Maxim 83 # Perminov, Maxim Locktyukhin and Jim Guilford of Intel. I've used 84 # some of the ideas even in attempt to optmize the original RC4_INT 85 # code path... Current performance in cycles per processed byte (less 86 # is better) and improvement coefficients relative to previous 87 # version of this module are: 88 # 89 # Opteron 5.3/+0%(*) 90 # P4 6.5 91 # Core2 6.2/+15%(**) 92 # Westmere 4.2/+60% 93 # Sandy Bridge 4.2/+120% 94 # Atom 9.3/+80% 95 # 96 # (*) But corresponding loop has less instructions, which should have 97 # positive effect on upcoming Bulldozer, which has one less ALU. 98 # For reference, Intel code runs at 6.8 cpb rate on Opteron. 99 # (**) Note that Core2 result is ~15% lower than corresponding result 100 # for 32-bit code, meaning that it's possible to improve it, 101 # but more than likely at the cost of the others (see rc4-586.pl 102 # to get the idea)... 103 104 $flavour = shift; 105 $output = shift; 106 if ($flavour =~ /\./) { $output = $flavour; undef $flavour; } 107 108 $win64=0; $win64=1 if ($flavour =~ /[nm]asm|mingw64/ || $output =~ /\.asm$/); 109 110 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 111 ( $xlate="${dir}x86_64-xlate.pl" and -f $xlate ) or 112 ( $xlate="${dir}../../perlasm/x86_64-xlate.pl" and -f $xlate) or 113 die "can't locate x86_64-xlate.pl"; 114 115 open OUT,"| \"$^X\" $xlate $flavour $output"; 116 *STDOUT=*OUT; 117 118 $dat="%rdi"; # arg1 119 $len="%rsi"; # arg2 120 $inp="%rdx"; # arg3 121 $out="%rcx"; # arg4 122 123 { 124 $code=<<___; 125 .text 126 .extern OPENSSL_ia32cap_P 127 128 .globl asm_RC4 129 .type asm_RC4,\@function,4 130 .align 16 131 asm_RC4: 132 or $len,$len 133 jne .Lentry 134 ret 135 .Lentry: 136 push %rbx 137 push %r12 138 push %r13 139 .Lprologue: 140 mov $len,%r11 141 mov $inp,%r12 142 mov $out,%r13 143 ___ 144 my $len="%r11"; # reassign input arguments 145 my $inp="%r12"; 146 my $out="%r13"; 147 148 my @XX=("%r10","%rsi"); 149 my @TX=("%rax","%rbx"); 150 my $YY="%rcx"; 151 my $TY="%rdx"; 152 153 $code.=<<___; 154 xor $XX[0],$XX[0] 155 xor $YY,$YY 156 157 lea 8($dat),$dat 158 mov -8($dat),$XX[0]#b 159 mov -4($dat),$YY#b 160 cmpl \$-1,256($dat) 161 je .LRC4_CHAR 162 mov OPENSSL_ia32cap_P\@GOTPCREL(%rip),%r8 163 mov (%r8),%r8d 164 xor $TX[1],$TX[1] 165 inc $XX[0]#b 166 sub $XX[0],$TX[1] 167 sub $inp,$out 168 movl ($dat,$XX[0],4),$TX[0]#d 169 test \$-16,$len 170 jz .Lloop1 171 bt \$30,%r8d # Intel CPU? 172 jc .Lintel 173 and \$7,$TX[1] 174 lea 1($XX[0]),$XX[1] 175 jz .Loop8 176 sub $TX[1],$len 177 .Loop8_warmup: 178 add $TX[0]#b,$YY#b 179 movl ($dat,$YY,4),$TY#d 180 movl $TX[0]#d,($dat,$YY,4) 181 movl $TY#d,($dat,$XX[0],4) 182 add $TY#b,$TX[0]#b 183 inc $XX[0]#b 184 movl ($dat,$TX[0],4),$TY#d 185 movl ($dat,$XX[0],4),$TX[0]#d 186 xorb ($inp),$TY#b 187 movb $TY#b,($out,$inp) 188 lea 1($inp),$inp 189 dec $TX[1] 190 jnz .Loop8_warmup 191 192 lea 1($XX[0]),$XX[1] 193 jmp .Loop8 194 .align 16 195 .Loop8: 196 ___ 197 for ($i=0;$i<8;$i++) { 198 $code.=<<___ if ($i==7); 199 add \$8,$XX[1]#b 200 ___ 201 $code.=<<___; 202 add $TX[0]#b,$YY#b 203 movl ($dat,$YY,4),$TY#d 204 movl $TX[0]#d,($dat,$YY,4) 205 movl `4*($i==7?-1:$i)`($dat,$XX[1],4),$TX[1]#d 206 ror \$8,%r8 # ror is redundant when $i=0 207 movl $TY#d,4*$i($dat,$XX[0],4) 208 add $TX[0]#b,$TY#b 209 movb ($dat,$TY,4),%r8b 210 ___ 211 push(@TX,shift(@TX)); #push(@XX,shift(@XX)); # "rotate" registers 212 } 213 $code.=<<___; 214 add \$8,$XX[0]#b 215 ror \$8,%r8 216 sub \$8,$len 217 218 xor ($inp),%r8 219 mov %r8,($out,$inp) 220 lea 8($inp),$inp 221 222 test \$-8,$len 223 jnz .Loop8 224 cmp \$0,$len 225 jne .Lloop1 226 jmp .Lexit 227 228 .align 16 229 .Lintel: 230 test \$-32,$len 231 jz .Lloop1 232 and \$15,$TX[1] 233 jz .Loop16_is_hot 234 sub $TX[1],$len 235 .Loop16_warmup: 236 add $TX[0]#b,$YY#b 237 movl ($dat,$YY,4),$TY#d 238 movl $TX[0]#d,($dat,$YY,4) 239 movl $TY#d,($dat,$XX[0],4) 240 add $TY#b,$TX[0]#b 241 inc $XX[0]#b 242 movl ($dat,$TX[0],4),$TY#d 243 movl ($dat,$XX[0],4),$TX[0]#d 244 xorb ($inp),$TY#b 245 movb $TY#b,($out,$inp) 246 lea 1($inp),$inp 247 dec $TX[1] 248 jnz .Loop16_warmup 249 250 mov $YY,$TX[1] 251 xor $YY,$YY 252 mov $TX[1]#b,$YY#b 253 254 .Loop16_is_hot: 255 lea ($dat,$XX[0],4),$XX[1] 256 ___ 257 sub RC4_loop { 258 my $i=shift; 259 my $j=$i<0?0:$i; 260 my $xmm="%xmm".($j&1); 261 262 $code.=" add \$16,$XX[0]#b\n" if ($i==15); 263 $code.=" movdqu ($inp),%xmm2\n" if ($i==15); 264 $code.=" add $TX[0]#b,$YY#b\n" if ($i<=0); 265 $code.=" movl ($dat,$YY,4),$TY#d\n"; 266 $code.=" pxor %xmm0,%xmm2\n" if ($i==0); 267 $code.=" psllq \$8,%xmm1\n" if ($i==0); 268 $code.=" pxor $xmm,$xmm\n" if ($i<=1); 269 $code.=" movl $TX[0]#d,($dat,$YY,4)\n"; 270 $code.=" add $TY#b,$TX[0]#b\n"; 271 $code.=" movl `4*($j+1)`($XX[1]),$TX[1]#d\n" if ($i<15); 272 $code.=" movz $TX[0]#b,$TX[0]#d\n"; 273 $code.=" movl $TY#d,4*$j($XX[1])\n"; 274 $code.=" pxor %xmm1,%xmm2\n" if ($i==0); 275 $code.=" lea ($dat,$XX[0],4),$XX[1]\n" if ($i==15); 276 $code.=" add $TX[1]#b,$YY#b\n" if ($i<15); 277 $code.=" pinsrw \$`($j>>1)&7`,($dat,$TX[0],4),$xmm\n"; 278 $code.=" movdqu %xmm2,($out,$inp)\n" if ($i==0); 279 $code.=" lea 16($inp),$inp\n" if ($i==0); 280 $code.=" movl ($XX[1]),$TX[1]#d\n" if ($i==15); 281 } 282 RC4_loop(-1); 283 $code.=<<___; 284 jmp .Loop16_enter 285 .align 16 286 .Loop16: 287 ___ 288 289 for ($i=0;$i<16;$i++) { 290 $code.=".Loop16_enter:\n" if ($i==1); 291 RC4_loop($i); 292 push(@TX,shift(@TX)); # "rotate" registers 293 } 294 $code.=<<___; 295 mov $YY,$TX[1] 296 xor $YY,$YY # keyword to partial register 297 sub \$16,$len 298 mov $TX[1]#b,$YY#b 299 test \$-16,$len 300 jnz .Loop16 301 302 psllq \$8,%xmm1 303 pxor %xmm0,%xmm2 304 pxor %xmm1,%xmm2 305 movdqu %xmm2,($out,$inp) 306 lea 16($inp),$inp 307 308 cmp \$0,$len 309 jne .Lloop1 310 jmp .Lexit 311 312 .align 16 313 .Lloop1: 314 add $TX[0]#b,$YY#b 315 movl ($dat,$YY,4),$TY#d 316 movl $TX[0]#d,($dat,$YY,4) 317 movl $TY#d,($dat,$XX[0],4) 318 add $TY#b,$TX[0]#b 319 inc $XX[0]#b 320 movl ($dat,$TX[0],4),$TY#d 321 movl ($dat,$XX[0],4),$TX[0]#d 322 xorb ($inp),$TY#b 323 movb $TY#b,($out,$inp) 324 lea 1($inp),$inp 325 dec $len 326 jnz .Lloop1 327 jmp .Lexit 328 329 .align 16 330 .LRC4_CHAR: 331 add \$1,$XX[0]#b 332 movzb ($dat,$XX[0]),$TX[0]#d 333 test \$-8,$len 334 jz .Lcloop1 335 jmp .Lcloop8 336 .align 16 337 .Lcloop8: 338 mov ($inp),%r8d 339 mov 4($inp),%r9d 340 ___ 341 # unroll 2x4-wise, because 64-bit rotates kill Intel P4... 342 for ($i=0;$i<4;$i++) { 343 $code.=<<___; 344 add $TX[0]#b,$YY#b 345 lea 1($XX[0]),$XX[1] 346 movzb ($dat,$YY),$TY#d 347 movzb $XX[1]#b,$XX[1]#d 348 movzb ($dat,$XX[1]),$TX[1]#d 349 movb $TX[0]#b,($dat,$YY) 350 cmp $XX[1],$YY 351 movb $TY#b,($dat,$XX[0]) 352 jne .Lcmov$i # Intel cmov is sloooow... 353 mov $TX[0],$TX[1] 354 .Lcmov$i: 355 add $TX[0]#b,$TY#b 356 xor ($dat,$TY),%r8b 357 ror \$8,%r8d 358 ___ 359 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers 360 } 361 for ($i=4;$i<8;$i++) { 362 $code.=<<___; 363 add $TX[0]#b,$YY#b 364 lea 1($XX[0]),$XX[1] 365 movzb ($dat,$YY),$TY#d 366 movzb $XX[1]#b,$XX[1]#d 367 movzb ($dat,$XX[1]),$TX[1]#d 368 movb $TX[0]#b,($dat,$YY) 369 cmp $XX[1],$YY 370 movb $TY#b,($dat,$XX[0]) 371 jne .Lcmov$i # Intel cmov is sloooow... 372 mov $TX[0],$TX[1] 373 .Lcmov$i: 374 add $TX[0]#b,$TY#b 375 xor ($dat,$TY),%r9b 376 ror \$8,%r9d 377 ___ 378 push(@TX,shift(@TX)); push(@XX,shift(@XX)); # "rotate" registers 379 } 380 $code.=<<___; 381 lea -8($len),$len 382 mov %r8d,($out) 383 lea 8($inp),$inp 384 mov %r9d,4($out) 385 lea 8($out),$out 386 387 test \$-8,$len 388 jnz .Lcloop8 389 cmp \$0,$len 390 jne .Lcloop1 391 jmp .Lexit 392 ___ 393 $code.=<<___; 394 .align 16 395 .Lcloop1: 396 add $TX[0]#b,$YY#b 397 movzb $YY#b,$YY#d 398 movzb ($dat,$YY),$TY#d 399 movb $TX[0]#b,($dat,$YY) 400 movb $TY#b,($dat,$XX[0]) 401 add $TX[0]#b,$TY#b 402 add \$1,$XX[0]#b 403 movzb $TY#b,$TY#d 404 movzb $XX[0]#b,$XX[0]#d 405 movzb ($dat,$TY),$TY#d 406 movzb ($dat,$XX[0]),$TX[0]#d 407 xorb ($inp),$TY#b 408 lea 1($inp),$inp 409 movb $TY#b,($out) 410 lea 1($out),$out 411 sub \$1,$len 412 jnz .Lcloop1 413 jmp .Lexit 414 415 .align 16 416 .Lexit: 417 sub \$1,$XX[0]#b 418 movl $XX[0]#d,-8($dat) 419 movl $YY#d,-4($dat) 420 421 mov (%rsp),%r13 422 mov 8(%rsp),%r12 423 mov 16(%rsp),%rbx 424 add \$24,%rsp 425 .Lepilogue: 426 ret 427 .size asm_RC4,.-asm_RC4 428 ___ 429 } 430 431 $idx="%r8"; 432 $ido="%r9"; 433 434 $code.=<<___; 435 .globl asm_RC4_set_key 436 .type asm_RC4_set_key,\@function,3 437 .align 16 438 asm_RC4_set_key: 439 lea 8($dat),$dat 440 lea ($inp,$len),$inp 441 neg $len 442 mov $len,%rcx 443 xor %eax,%eax 444 xor $ido,$ido 445 xor %r10,%r10 446 xor %r11,%r11 447 448 mov OPENSSL_ia32cap_P\@GOTPCREL(%rip),$idx 449 mov ($idx),$idx#d 450 bt \$20,$idx#d # RC4_CHAR? 451 jc .Lc1stloop 452 jmp .Lw1stloop 453 454 .align 16 455 .Lw1stloop: 456 mov %eax,($dat,%rax,4) 457 add \$1,%al 458 jnc .Lw1stloop 459 460 xor $ido,$ido 461 xor $idx,$idx 462 .align 16 463 .Lw2ndloop: 464 mov ($dat,$ido,4),%r10d 465 add ($inp,$len,1),$idx#b 466 add %r10b,$idx#b 467 add \$1,$len 468 mov ($dat,$idx,4),%r11d 469 cmovz %rcx,$len 470 mov %r10d,($dat,$idx,4) 471 mov %r11d,($dat,$ido,4) 472 add \$1,$ido#b 473 jnc .Lw2ndloop 474 jmp .Lexit_key 475 476 .align 16 477 .Lc1stloop: 478 mov %al,($dat,%rax) 479 add \$1,%al 480 jnc .Lc1stloop 481 482 xor $ido,$ido 483 xor $idx,$idx 484 .align 16 485 .Lc2ndloop: 486 mov ($dat,$ido),%r10b 487 add ($inp,$len),$idx#b 488 add %r10b,$idx#b 489 add \$1,$len 490 mov ($dat,$idx),%r11b 491 jnz .Lcnowrap 492 mov %rcx,$len 493 .Lcnowrap: 494 mov %r10b,($dat,$idx) 495 mov %r11b,($dat,$ido) 496 add \$1,$ido#b 497 jnc .Lc2ndloop 498 movl \$-1,256($dat) 499 500 .align 16 501 .Lexit_key: 502 xor %eax,%eax 503 mov %eax,-8($dat) 504 mov %eax,-4($dat) 505 ret 506 .size asm_RC4_set_key,.-asm_RC4_set_key 507 508 .globl RC4_options 509 .type RC4_options,\@abi-omnipotent 510 .align 16 511 RC4_options: 512 lea .Lopts(%rip),%rax 513 mov OPENSSL_ia32cap_P(%rip),%rdx 514 mov (%rdx),%edx 515 bt \$20,%edx 516 jc .L8xchar 517 bt \$30,%edx 518 jnc .Ldone 519 add \$25,%rax 520 ret 521 .L8xchar: 522 add \$12,%rax 523 .Ldone: 524 ret 525 .align 64 526 .Lopts: 527 .asciz "rc4(8x,int)" 528 .asciz "rc4(8x,char)" 529 .asciz "rc4(16x,int)" 530 .asciz "RC4 for x86_64, CRYPTOGAMS by <appro\@openssl.org>" 531 .align 64 532 .size RC4_options,.-RC4_options 533 ___ 534 535 # EXCEPTION_DISPOSITION handler (EXCEPTION_RECORD *rec,ULONG64 frame, 536 # CONTEXT *context,DISPATCHER_CONTEXT *disp) 537 if ($win64) { 538 $rec="%rcx"; 539 $frame="%rdx"; 540 $context="%r8"; 541 $disp="%r9"; 542 543 $code.=<<___; 544 .extern __imp_RtlVirtualUnwind 545 .type stream_se_handler,\@abi-omnipotent 546 .align 16 547 stream_se_handler: 548 push %rsi 549 push %rdi 550 push %rbx 551 push %rbp 552 push %r12 553 push %r13 554 push %r14 555 push %r15 556 pushfq 557 sub \$64,%rsp 558 559 mov 120($context),%rax # pull context->Rax 560 mov 248($context),%rbx # pull context->Rip 561 562 lea .Lprologue(%rip),%r10 563 cmp %r10,%rbx # context->Rip<prologue label 564 jb .Lin_prologue 565 566 mov 152($context),%rax # pull context->Rsp 567 568 lea .Lepilogue(%rip),%r10 569 cmp %r10,%rbx # context->Rip>=epilogue label 570 jae .Lin_prologue 571 572 lea 24(%rax),%rax 573 574 mov -8(%rax),%rbx 575 mov -16(%rax),%r12 576 mov -24(%rax),%r13 577 mov %rbx,144($context) # restore context->Rbx 578 mov %r12,216($context) # restore context->R12 579 mov %r13,224($context) # restore context->R13 580 581 .Lin_prologue: 582 mov 8(%rax),%rdi 583 mov 16(%rax),%rsi 584 mov %rax,152($context) # restore context->Rsp 585 mov %rsi,168($context) # restore context->Rsi 586 mov %rdi,176($context) # restore context->Rdi 587 588 jmp .Lcommon_seh_exit 589 .size stream_se_handler,.-stream_se_handler 590 591 .type key_se_handler,\@abi-omnipotent 592 .align 16 593 key_se_handler: 594 push %rsi 595 push %rdi 596 push %rbx 597 push %rbp 598 push %r12 599 push %r13 600 push %r14 601 push %r15 602 pushfq 603 sub \$64,%rsp 604 605 mov 152($context),%rax # pull context->Rsp 606 mov 8(%rax),%rdi 607 mov 16(%rax),%rsi 608 mov %rsi,168($context) # restore context->Rsi 609 mov %rdi,176($context) # restore context->Rdi 610 611 .Lcommon_seh_exit: 612 613 mov 40($disp),%rdi # disp->ContextRecord 614 mov $context,%rsi # context 615 mov \$154,%ecx # sizeof(CONTEXT) 616 .long 0xa548f3fc # cld; rep movsq 617 618 mov $disp,%rsi 619 xor %rcx,%rcx # arg1, UNW_FLAG_NHANDLER 620 mov 8(%rsi),%rdx # arg2, disp->ImageBase 621 mov 0(%rsi),%r8 # arg3, disp->ControlPc 622 mov 16(%rsi),%r9 # arg4, disp->FunctionEntry 623 mov 40(%rsi),%r10 # disp->ContextRecord 624 lea 56(%rsi),%r11 # &disp->HandlerData 625 lea 24(%rsi),%r12 # &disp->EstablisherFrame 626 mov %r10,32(%rsp) # arg5 627 mov %r11,40(%rsp) # arg6 628 mov %r12,48(%rsp) # arg7 629 mov %rcx,56(%rsp) # arg8, (NULL) 630 call *__imp_RtlVirtualUnwind(%rip) 631 632 mov \$1,%eax # ExceptionContinueSearch 633 add \$64,%rsp 634 popfq 635 pop %r15 636 pop %r14 637 pop %r13 638 pop %r12 639 pop %rbp 640 pop %rbx 641 pop %rdi 642 pop %rsi 643 ret 644 .size key_se_handler,.-key_se_handler 645 646 .section .pdata 647 .align 4 648 .rva .LSEH_begin_asm_RC4 649 .rva .LSEH_end_asm_RC4 650 .rva .LSEH_info_asm_RC4 651 652 .rva .LSEH_begin_asm_RC4_set_key 653 .rva .LSEH_end_asm_RC4_set_key 654 .rva .LSEH_info_asm_RC4_set_key 655 656 .section .xdata 657 .align 8 658 .LSEH_info_asm_RC4: 659 .byte 9,0,0,0 660 .rva stream_se_handler 661 .LSEH_info_asm_RC4_set_key: 662 .byte 9,0,0,0 663 .rva key_se_handler 664 ___ 665 } 666 667 sub reg_part { 668 my ($reg,$conv)=@_; 669 if ($reg =~ /%r[0-9]+/) { $reg .= $conv; } 670 elsif ($conv eq "b") { $reg =~ s/%[er]([^x]+)x?/%$1l/; } 671 elsif ($conv eq "w") { $reg =~ s/%[er](.+)/%$1/; } 672 elsif ($conv eq "d") { $reg =~ s/%[er](.+)/%e$1/; } 673 return $reg; 674 } 675 676 $code =~ s/(%[a-z0-9]+)#([bwd])/reg_part($1,$2)/gem; 677 $code =~ s/\`([^\`]*)\`/eval $1/gem; 678 679 print $code; 680 681 close STDOUT; 682
