1 /* 2 * vmx.h: VMX Architecture related definitions 3 * Copyright (c) 2004, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple 16 * Place - Suite 330, Boston, MA 02111-1307 USA. 17 * 18 * A few random additions are: 19 * Copyright (C) 2006 Qumranet 20 * Avi Kivity <avi (at) qumranet.com> 21 * Yaniv Kamay <yaniv (at) qumranet.com> 22 * 23 */ 24 #ifndef VMX_H 25 #define VMX_H 26 27 28 #include <linux/types.h> 29 #include <uapi/asm/vmx.h> 30 31 /* 32 * Definitions of Primary Processor-Based VM-Execution Controls. 33 */ 34 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004 35 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008 36 #define CPU_BASED_HLT_EXITING 0x00000080 37 #define CPU_BASED_INVLPG_EXITING 0x00000200 38 #define CPU_BASED_MWAIT_EXITING 0x00000400 39 #define CPU_BASED_RDPMC_EXITING 0x00000800 40 #define CPU_BASED_RDTSC_EXITING 0x00001000 41 #define CPU_BASED_CR3_LOAD_EXITING 0x00008000 42 #define CPU_BASED_CR3_STORE_EXITING 0x00010000 43 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000 44 #define CPU_BASED_CR8_STORE_EXITING 0x00100000 45 #define CPU_BASED_TPR_SHADOW 0x00200000 46 #define CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000 47 #define CPU_BASED_MOV_DR_EXITING 0x00800000 48 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000 49 #define CPU_BASED_USE_IO_BITMAPS 0x02000000 50 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000 51 #define CPU_BASED_MONITOR_EXITING 0x20000000 52 #define CPU_BASED_PAUSE_EXITING 0x40000000 53 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000 54 /* 55 * Definitions of Secondary Processor-Based VM-Execution Controls. 56 */ 57 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001 58 #define SECONDARY_EXEC_ENABLE_EPT 0x00000002 59 #define SECONDARY_EXEC_RDTSCP 0x00000008 60 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010 61 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020 62 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040 63 #define SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080 64 #define SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100 65 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200 66 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400 67 #define SECONDARY_EXEC_ENABLE_INVPCID 0x00001000 68 #define SECONDARY_EXEC_SHADOW_VMCS 0x00004000 69 70 71 #define PIN_BASED_EXT_INTR_MASK 0x00000001 72 #define PIN_BASED_NMI_EXITING 0x00000008 73 #define PIN_BASED_VIRTUAL_NMIS 0x00000020 74 #define PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040 75 #define PIN_BASED_POSTED_INTR 0x00000080 76 77 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016 78 79 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000002 80 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200 81 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000 82 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000 83 #define VM_EXIT_SAVE_IA32_PAT 0x00040000 84 #define VM_EXIT_LOAD_IA32_PAT 0x00080000 85 #define VM_EXIT_SAVE_IA32_EFER 0x00100000 86 #define VM_EXIT_LOAD_IA32_EFER 0x00200000 87 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000 88 89 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff 90 91 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000002 92 #define VM_ENTRY_IA32E_MODE 0x00000200 93 #define VM_ENTRY_SMM 0x00000400 94 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800 95 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000 96 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000 97 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000 98 99 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff 100 101 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f 102 #define VMX_MISC_SAVE_EFER_LMA 0x00000020 103 104 /* VMCS Encodings */ 105 enum vmcs_field { 106 VIRTUAL_PROCESSOR_ID = 0x00000000, 107 POSTED_INTR_NV = 0x00000002, 108 GUEST_ES_SELECTOR = 0x00000800, 109 GUEST_CS_SELECTOR = 0x00000802, 110 GUEST_SS_SELECTOR = 0x00000804, 111 GUEST_DS_SELECTOR = 0x00000806, 112 GUEST_FS_SELECTOR = 0x00000808, 113 GUEST_GS_SELECTOR = 0x0000080a, 114 GUEST_LDTR_SELECTOR = 0x0000080c, 115 GUEST_TR_SELECTOR = 0x0000080e, 116 GUEST_INTR_STATUS = 0x00000810, 117 HOST_ES_SELECTOR = 0x00000c00, 118 HOST_CS_SELECTOR = 0x00000c02, 119 HOST_SS_SELECTOR = 0x00000c04, 120 HOST_DS_SELECTOR = 0x00000c06, 121 HOST_FS_SELECTOR = 0x00000c08, 122 HOST_GS_SELECTOR = 0x00000c0a, 123 HOST_TR_SELECTOR = 0x00000c0c, 124 IO_BITMAP_A = 0x00002000, 125 IO_BITMAP_A_HIGH = 0x00002001, 126 IO_BITMAP_B = 0x00002002, 127 IO_BITMAP_B_HIGH = 0x00002003, 128 MSR_BITMAP = 0x00002004, 129 MSR_BITMAP_HIGH = 0x00002005, 130 VM_EXIT_MSR_STORE_ADDR = 0x00002006, 131 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007, 132 VM_EXIT_MSR_LOAD_ADDR = 0x00002008, 133 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009, 134 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a, 135 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b, 136 TSC_OFFSET = 0x00002010, 137 TSC_OFFSET_HIGH = 0x00002011, 138 VIRTUAL_APIC_PAGE_ADDR = 0x00002012, 139 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013, 140 APIC_ACCESS_ADDR = 0x00002014, 141 APIC_ACCESS_ADDR_HIGH = 0x00002015, 142 POSTED_INTR_DESC_ADDR = 0x00002016, 143 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017, 144 EPT_POINTER = 0x0000201a, 145 EPT_POINTER_HIGH = 0x0000201b, 146 EOI_EXIT_BITMAP0 = 0x0000201c, 147 EOI_EXIT_BITMAP0_HIGH = 0x0000201d, 148 EOI_EXIT_BITMAP1 = 0x0000201e, 149 EOI_EXIT_BITMAP1_HIGH = 0x0000201f, 150 EOI_EXIT_BITMAP2 = 0x00002020, 151 EOI_EXIT_BITMAP2_HIGH = 0x00002021, 152 EOI_EXIT_BITMAP3 = 0x00002022, 153 EOI_EXIT_BITMAP3_HIGH = 0x00002023, 154 VMREAD_BITMAP = 0x00002026, 155 VMWRITE_BITMAP = 0x00002028, 156 GUEST_PHYSICAL_ADDRESS = 0x00002400, 157 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401, 158 VMCS_LINK_POINTER = 0x00002800, 159 VMCS_LINK_POINTER_HIGH = 0x00002801, 160 GUEST_IA32_DEBUGCTL = 0x00002802, 161 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803, 162 GUEST_IA32_PAT = 0x00002804, 163 GUEST_IA32_PAT_HIGH = 0x00002805, 164 GUEST_IA32_EFER = 0x00002806, 165 GUEST_IA32_EFER_HIGH = 0x00002807, 166 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808, 167 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809, 168 GUEST_PDPTR0 = 0x0000280a, 169 GUEST_PDPTR0_HIGH = 0x0000280b, 170 GUEST_PDPTR1 = 0x0000280c, 171 GUEST_PDPTR1_HIGH = 0x0000280d, 172 GUEST_PDPTR2 = 0x0000280e, 173 GUEST_PDPTR2_HIGH = 0x0000280f, 174 GUEST_PDPTR3 = 0x00002810, 175 GUEST_PDPTR3_HIGH = 0x00002811, 176 HOST_IA32_PAT = 0x00002c00, 177 HOST_IA32_PAT_HIGH = 0x00002c01, 178 HOST_IA32_EFER = 0x00002c02, 179 HOST_IA32_EFER_HIGH = 0x00002c03, 180 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04, 181 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05, 182 PIN_BASED_VM_EXEC_CONTROL = 0x00004000, 183 CPU_BASED_VM_EXEC_CONTROL = 0x00004002, 184 EXCEPTION_BITMAP = 0x00004004, 185 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006, 186 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008, 187 CR3_TARGET_COUNT = 0x0000400a, 188 VM_EXIT_CONTROLS = 0x0000400c, 189 VM_EXIT_MSR_STORE_COUNT = 0x0000400e, 190 VM_EXIT_MSR_LOAD_COUNT = 0x00004010, 191 VM_ENTRY_CONTROLS = 0x00004012, 192 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014, 193 VM_ENTRY_INTR_INFO_FIELD = 0x00004016, 194 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018, 195 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a, 196 TPR_THRESHOLD = 0x0000401c, 197 SECONDARY_VM_EXEC_CONTROL = 0x0000401e, 198 PLE_GAP = 0x00004020, 199 PLE_WINDOW = 0x00004022, 200 VM_INSTRUCTION_ERROR = 0x00004400, 201 VM_EXIT_REASON = 0x00004402, 202 VM_EXIT_INTR_INFO = 0x00004404, 203 VM_EXIT_INTR_ERROR_CODE = 0x00004406, 204 IDT_VECTORING_INFO_FIELD = 0x00004408, 205 IDT_VECTORING_ERROR_CODE = 0x0000440a, 206 VM_EXIT_INSTRUCTION_LEN = 0x0000440c, 207 VMX_INSTRUCTION_INFO = 0x0000440e, 208 GUEST_ES_LIMIT = 0x00004800, 209 GUEST_CS_LIMIT = 0x00004802, 210 GUEST_SS_LIMIT = 0x00004804, 211 GUEST_DS_LIMIT = 0x00004806, 212 GUEST_FS_LIMIT = 0x00004808, 213 GUEST_GS_LIMIT = 0x0000480a, 214 GUEST_LDTR_LIMIT = 0x0000480c, 215 GUEST_TR_LIMIT = 0x0000480e, 216 GUEST_GDTR_LIMIT = 0x00004810, 217 GUEST_IDTR_LIMIT = 0x00004812, 218 GUEST_ES_AR_BYTES = 0x00004814, 219 GUEST_CS_AR_BYTES = 0x00004816, 220 GUEST_SS_AR_BYTES = 0x00004818, 221 GUEST_DS_AR_BYTES = 0x0000481a, 222 GUEST_FS_AR_BYTES = 0x0000481c, 223 GUEST_GS_AR_BYTES = 0x0000481e, 224 GUEST_LDTR_AR_BYTES = 0x00004820, 225 GUEST_TR_AR_BYTES = 0x00004822, 226 GUEST_INTERRUPTIBILITY_INFO = 0x00004824, 227 GUEST_ACTIVITY_STATE = 0X00004826, 228 GUEST_SYSENTER_CS = 0x0000482A, 229 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E, 230 HOST_IA32_SYSENTER_CS = 0x00004c00, 231 CR0_GUEST_HOST_MASK = 0x00006000, 232 CR4_GUEST_HOST_MASK = 0x00006002, 233 CR0_READ_SHADOW = 0x00006004, 234 CR4_READ_SHADOW = 0x00006006, 235 CR3_TARGET_VALUE0 = 0x00006008, 236 CR3_TARGET_VALUE1 = 0x0000600a, 237 CR3_TARGET_VALUE2 = 0x0000600c, 238 CR3_TARGET_VALUE3 = 0x0000600e, 239 EXIT_QUALIFICATION = 0x00006400, 240 GUEST_LINEAR_ADDRESS = 0x0000640a, 241 GUEST_CR0 = 0x00006800, 242 GUEST_CR3 = 0x00006802, 243 GUEST_CR4 = 0x00006804, 244 GUEST_ES_BASE = 0x00006806, 245 GUEST_CS_BASE = 0x00006808, 246 GUEST_SS_BASE = 0x0000680a, 247 GUEST_DS_BASE = 0x0000680c, 248 GUEST_FS_BASE = 0x0000680e, 249 GUEST_GS_BASE = 0x00006810, 250 GUEST_LDTR_BASE = 0x00006812, 251 GUEST_TR_BASE = 0x00006814, 252 GUEST_GDTR_BASE = 0x00006816, 253 GUEST_IDTR_BASE = 0x00006818, 254 GUEST_DR7 = 0x0000681a, 255 GUEST_RSP = 0x0000681c, 256 GUEST_RIP = 0x0000681e, 257 GUEST_RFLAGS = 0x00006820, 258 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822, 259 GUEST_SYSENTER_ESP = 0x00006824, 260 GUEST_SYSENTER_EIP = 0x00006826, 261 HOST_CR0 = 0x00006c00, 262 HOST_CR3 = 0x00006c02, 263 HOST_CR4 = 0x00006c04, 264 HOST_FS_BASE = 0x00006c06, 265 HOST_GS_BASE = 0x00006c08, 266 HOST_TR_BASE = 0x00006c0a, 267 HOST_GDTR_BASE = 0x00006c0c, 268 HOST_IDTR_BASE = 0x00006c0e, 269 HOST_IA32_SYSENTER_ESP = 0x00006c10, 270 HOST_IA32_SYSENTER_EIP = 0x00006c12, 271 HOST_RSP = 0x00006c14, 272 HOST_RIP = 0x00006c16, 273 }; 274 275 /* 276 * Interruption-information format 277 */ 278 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */ 279 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */ 280 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */ 281 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */ 282 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */ 283 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000 284 285 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK 286 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK 287 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK 288 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK 289 290 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */ 291 #define INTR_TYPE_NMI_INTR (2 << 8) /* NMI */ 292 #define INTR_TYPE_HARD_EXCEPTION (3 << 8) /* processor exception */ 293 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */ 294 #define INTR_TYPE_SOFT_EXCEPTION (6 << 8) /* software exception */ 295 296 /* GUEST_INTERRUPTIBILITY_INFO flags. */ 297 #define GUEST_INTR_STATE_STI 0x00000001 298 #define GUEST_INTR_STATE_MOV_SS 0x00000002 299 #define GUEST_INTR_STATE_SMI 0x00000004 300 #define GUEST_INTR_STATE_NMI 0x00000008 301 302 /* GUEST_ACTIVITY_STATE flags */ 303 #define GUEST_ACTIVITY_ACTIVE 0 304 #define GUEST_ACTIVITY_HLT 1 305 #define GUEST_ACTIVITY_SHUTDOWN 2 306 #define GUEST_ACTIVITY_WAIT_SIPI 3 307 308 /* 309 * Exit Qualifications for MOV for Control Register Access 310 */ 311 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/ 312 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */ 313 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */ 314 #define LMSW_SOURCE_DATA_SHIFT 16 315 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */ 316 #define REG_EAX (0 << 8) 317 #define REG_ECX (1 << 8) 318 #define REG_EDX (2 << 8) 319 #define REG_EBX (3 << 8) 320 #define REG_ESP (4 << 8) 321 #define REG_EBP (5 << 8) 322 #define REG_ESI (6 << 8) 323 #define REG_EDI (7 << 8) 324 #define REG_R8 (8 << 8) 325 #define REG_R9 (9 << 8) 326 #define REG_R10 (10 << 8) 327 #define REG_R11 (11 << 8) 328 #define REG_R12 (12 << 8) 329 #define REG_R13 (13 << 8) 330 #define REG_R14 (14 << 8) 331 #define REG_R15 (15 << 8) 332 333 /* 334 * Exit Qualifications for MOV for Debug Register Access 335 */ 336 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */ 337 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */ 338 #define TYPE_MOV_TO_DR (0 << 4) 339 #define TYPE_MOV_FROM_DR (1 << 4) 340 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */ 341 342 343 /* 344 * Exit Qualifications for APIC-Access 345 */ 346 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */ 347 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */ 348 #define TYPE_LINEAR_APIC_INST_READ (0 << 12) 349 #define TYPE_LINEAR_APIC_INST_WRITE (1 << 12) 350 #define TYPE_LINEAR_APIC_INST_FETCH (2 << 12) 351 #define TYPE_LINEAR_APIC_EVENT (3 << 12) 352 #define TYPE_PHYSICAL_APIC_EVENT (10 << 12) 353 #define TYPE_PHYSICAL_APIC_INST (15 << 12) 354 355 /* segment AR */ 356 #define SEGMENT_AR_L_MASK (1 << 13) 357 358 #define AR_TYPE_ACCESSES_MASK 1 359 #define AR_TYPE_READABLE_MASK (1 << 1) 360 #define AR_TYPE_WRITEABLE_MASK (1 << 2) 361 #define AR_TYPE_CODE_MASK (1 << 3) 362 #define AR_TYPE_MASK 0x0f 363 #define AR_TYPE_BUSY_64_TSS 11 364 #define AR_TYPE_BUSY_32_TSS 11 365 #define AR_TYPE_BUSY_16_TSS 3 366 #define AR_TYPE_LDT 2 367 368 #define AR_UNUSABLE_MASK (1 << 16) 369 #define AR_S_MASK (1 << 4) 370 #define AR_P_MASK (1 << 7) 371 #define AR_L_MASK (1 << 13) 372 #define AR_DB_MASK (1 << 14) 373 #define AR_G_MASK (1 << 15) 374 #define AR_DPL_SHIFT 5 375 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3) 376 377 #define AR_RESERVD_MASK 0xfffe0f00 378 379 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0) 380 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 1) 381 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 2) 382 383 #define VMX_NR_VPIDS (1 << 16) 384 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1 385 #define VMX_VPID_EXTENT_ALL_CONTEXT 2 386 387 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR 0 388 #define VMX_EPT_EXTENT_CONTEXT 1 389 #define VMX_EPT_EXTENT_GLOBAL 2 390 #define VMX_EPT_EXTENT_SHIFT 24 391 392 #define VMX_EPT_EXECUTE_ONLY_BIT (1ull) 393 #define VMX_EPT_PAGE_WALK_4_BIT (1ull << 6) 394 #define VMX_EPTP_UC_BIT (1ull << 8) 395 #define VMX_EPTP_WB_BIT (1ull << 14) 396 #define VMX_EPT_2MB_PAGE_BIT (1ull << 16) 397 #define VMX_EPT_1GB_PAGE_BIT (1ull << 17) 398 #define VMX_EPT_INVEPT_BIT (1ull << 20) 399 #define VMX_EPT_AD_BIT (1ull << 21) 400 #define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25) 401 #define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26) 402 403 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT (1ull << 9) /* (41 - 32) */ 404 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT (1ull << 10) /* (42 - 32) */ 405 406 #define VMX_EPT_DEFAULT_GAW 3 407 #define VMX_EPT_MAX_GAW 0x4 408 #define VMX_EPT_MT_EPTE_SHIFT 3 409 #define VMX_EPT_GAW_EPTP_SHIFT 3 410 #define VMX_EPT_AD_ENABLE_BIT (1ull << 6) 411 #define VMX_EPT_DEFAULT_MT 0x6ull 412 #define VMX_EPT_READABLE_MASK 0x1ull 413 #define VMX_EPT_WRITABLE_MASK 0x2ull 414 #define VMX_EPT_EXECUTABLE_MASK 0x4ull 415 #define VMX_EPT_IPAT_BIT (1ull << 6) 416 #define VMX_EPT_ACCESS_BIT (1ull << 8) 417 #define VMX_EPT_DIRTY_BIT (1ull << 9) 418 419 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul 420 421 422 #define ASM_VMX_VMCLEAR_RAX ".byte 0x66, 0x0f, 0xc7, 0x30" 423 #define ASM_VMX_VMLAUNCH ".byte 0x0f, 0x01, 0xc2" 424 #define ASM_VMX_VMRESUME ".byte 0x0f, 0x01, 0xc3" 425 #define ASM_VMX_VMPTRLD_RAX ".byte 0x0f, 0xc7, 0x30" 426 #define ASM_VMX_VMREAD_RDX_RAX ".byte 0x0f, 0x78, 0xd0" 427 #define ASM_VMX_VMWRITE_RAX_RDX ".byte 0x0f, 0x79, 0xd0" 428 #define ASM_VMX_VMWRITE_RSP_RDX ".byte 0x0f, 0x79, 0xd4" 429 #define ASM_VMX_VMXOFF ".byte 0x0f, 0x01, 0xc4" 430 #define ASM_VMX_VMXON_RAX ".byte 0xf3, 0x0f, 0xc7, 0x30" 431 #define ASM_VMX_INVEPT ".byte 0x66, 0x0f, 0x38, 0x80, 0x08" 432 #define ASM_VMX_INVVPID ".byte 0x66, 0x0f, 0x38, 0x81, 0x08" 433 434 struct vmx_msr_entry { 435 u32 index; 436 u32 reserved; 437 u64 value; 438 } __aligned(16); 439 440 /* 441 * Exit Qualifications for entry failure during or after loading guest state 442 */ 443 #define ENTRY_FAIL_DEFAULT 0 444 #define ENTRY_FAIL_PDPTE 2 445 #define ENTRY_FAIL_NMI 3 446 #define ENTRY_FAIL_VMCS_LINK_PTR 4 447 448 /* 449 * VM-instruction error numbers 450 */ 451 enum vm_instruction_error_number { 452 VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1, 453 VMXERR_VMCLEAR_INVALID_ADDRESS = 2, 454 VMXERR_VMCLEAR_VMXON_POINTER = 3, 455 VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4, 456 VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5, 457 VMXERR_VMRESUME_AFTER_VMXOFF = 6, 458 VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7, 459 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8, 460 VMXERR_VMPTRLD_INVALID_ADDRESS = 9, 461 VMXERR_VMPTRLD_VMXON_POINTER = 10, 462 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11, 463 VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12, 464 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13, 465 VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15, 466 VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16, 467 VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17, 468 VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18, 469 VMXERR_VMCALL_NONCLEAR_VMCS = 19, 470 VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20, 471 VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22, 472 VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23, 473 VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24, 474 VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25, 475 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26, 476 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28, 477 }; 478 479 #endif 480
