1 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This describes the calling conventions for ARM architecture. 10 //===----------------------------------------------------------------------===// 11 12 /// CCIfAlign - Match of the original alignment of the arg 13 class CCIfAlign<string Align, CCAction A>: 14 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>; 15 16 //===----------------------------------------------------------------------===// 17 // ARM APCS Calling Convention 18 //===----------------------------------------------------------------------===// 19 def CC_ARM_APCS : CallingConv<[ 20 21 // Handles byval parameters. 22 CCIfByVal<CCPassByVal<4, 4>>, 23 24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 25 26 // Handle all vector types as either f64 or v2f64. 27 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 28 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 29 30 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack 31 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>, 32 33 CCIfType<[f32], CCBitConvertToType<i32>>, 34 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 35 36 CCIfType<[i32], CCAssignToStack<4, 4>>, 37 CCIfType<[f64], CCAssignToStack<8, 4>>, 38 CCIfType<[v2f64], CCAssignToStack<16, 4>> 39 ]>; 40 41 def RetCC_ARM_APCS : CallingConv<[ 42 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 43 CCIfType<[f32], CCBitConvertToType<i32>>, 44 45 // Handle all vector types as either f64 or v2f64. 46 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 47 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 48 49 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>, 50 51 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 52 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 53 ]>; 54 55 //===----------------------------------------------------------------------===// 56 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available) 57 //===----------------------------------------------------------------------===// 58 def FastCC_ARM_APCS : CallingConv<[ 59 // Handle all vector types as either f64 or v2f64. 60 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 61 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 62 63 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 64 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 65 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 66 S9, S10, S11, S12, S13, S14, S15]>>, 67 68 // CPRCs may be allocated to co-processor registers or the stack - they 69 // may never be allocated to core registers. 70 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 71 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>, 72 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>, 73 74 CCDelegateTo<CC_ARM_APCS> 75 ]>; 76 77 def RetFastCC_ARM_APCS : CallingConv<[ 78 // Handle all vector types as either f64 or v2f64. 79 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 80 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 81 82 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 83 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 84 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 85 S9, S10, S11, S12, S13, S14, S15]>>, 86 CCDelegateTo<RetCC_ARM_APCS> 87 ]>; 88 89 //===----------------------------------------------------------------------===// 90 // ARM APCS Calling Convention for GHC 91 //===----------------------------------------------------------------------===// 92 93 def CC_ARM_APCS_GHC : CallingConv<[ 94 // Handle all vector types as either f64 or v2f64. 95 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 96 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 97 98 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, 99 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, 100 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, 101 102 // Promote i8/i16 arguments to i32. 103 CCIfType<[i8, i16], CCPromoteToType<i32>>, 104 105 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim 106 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>> 107 ]>; 108 109 //===----------------------------------------------------------------------===// 110 // ARM AAPCS (EABI) Calling Convention, common parts 111 //===----------------------------------------------------------------------===// 112 113 def CC_ARM_AAPCS_Common : CallingConv<[ 114 115 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 116 117 // i64/f64 is passed in even pairs of GPRs 118 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register 119 // (and the same is true for f64 if VFP is not enabled) 120 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>, 121 CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8", 122 CCAssignToReg<[R0, R1, R2, R3]>>>, 123 124 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>, 125 CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>, 126 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 127 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>, 128 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>> 129 ]>; 130 131 def RetCC_ARM_AAPCS_Common : CallingConv<[ 132 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 133 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>, 134 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>> 135 ]>; 136 137 //===----------------------------------------------------------------------===// 138 // ARM AAPCS (EABI) Calling Convention 139 //===----------------------------------------------------------------------===// 140 141 def CC_ARM_AAPCS : CallingConv<[ 142 // Handles byval parameters. 143 CCIfByVal<CCPassByVal<4, 4>>, 144 145 // Handle all vector types as either f64 or v2f64. 146 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 147 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 148 149 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>, 150 CCIfType<[f32], CCBitConvertToType<i32>>, 151 CCDelegateTo<CC_ARM_AAPCS_Common> 152 ]>; 153 154 def RetCC_ARM_AAPCS : CallingConv<[ 155 // Handle all vector types as either f64 or v2f64. 156 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 157 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 158 159 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>, 160 CCIfType<[f32], CCBitConvertToType<i32>>, 161 CCDelegateTo<RetCC_ARM_AAPCS_Common> 162 ]>; 163 164 //===----------------------------------------------------------------------===// 165 // ARM AAPCS-VFP (EABI) Calling Convention 166 // Also used for FastCC (when VFP2 or later is available) 167 //===----------------------------------------------------------------------===// 168 169 def CC_ARM_AAPCS_VFP : CallingConv<[ 170 // Handles byval parameters. 171 CCIfByVal<CCPassByVal<4, 4>>, 172 173 // Handle all vector types as either f64 or v2f64. 174 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 175 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 176 177 // HFAs are passed in a contiguous block of registers, or on the stack 178 CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_HA">>, 179 180 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 181 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 182 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 183 S9, S10, S11, S12, S13, S14, S15]>>, 184 CCDelegateTo<CC_ARM_AAPCS_Common> 185 ]>; 186 187 def RetCC_ARM_AAPCS_VFP : CallingConv<[ 188 // Handle all vector types as either f64 or v2f64. 189 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>, 190 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>, 191 192 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 193 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>, 194 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8, 195 S9, S10, S11, S12, S13, S14, S15]>>, 196 CCDelegateTo<RetCC_ARM_AAPCS_Common> 197 ]>; 198 199 //===----------------------------------------------------------------------===// 200 // Callee-saved register lists. 201 //===----------------------------------------------------------------------===// 202 203 def CSR_NoRegs : CalleeSavedRegs<(add)>; 204 205 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4, 206 (sequence "D%u", 15, 8))>; 207 208 // Constructors and destructors return 'this' in the ARM C++ ABI; since 'this' 209 // and the pointer return value are both passed in R0 in these cases, this can 210 // be partially modelled by treating R0 as a callee-saved register 211 // Only the resulting RegMask is used; the SaveList is ignored 212 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, 213 R5, R4, (sequence "D%u", 15, 8), 214 R0)>; 215 216 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register. 217 // Also save R7-R4 first to match the stack frame fixed spill areas. 218 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>; 219 220 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4, 221 (sub CSR_AAPCS_ThisReturn, R9))>; 222 223 // The "interrupt" attribute is used to generate code that is acceptable in 224 // exception-handlers of various kinds. It makes us use a different return 225 // instruction (handled elsewhere) and affects which registers we must return to 226 // our "caller" in the same state as we receive them. 227 228 // For most interrupts, all registers except SP and LR are shared with 229 // user-space. We mark LR to be saved anyway, since this is what the ARM backend 230 // generally does rather than tracking its liveness as a normal register. 231 def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>; 232 233 // The fast interrupt handlers have more private state and get their own copies 234 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too. 235 236 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and 237 // current frame lowering expects to encounter it while processing callee-saved 238 // registers. 239 def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>; 240 241 242
