1 //===-- X86InstrFMA.td - FMA Instruction Set ---------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes FMA (Fused Multiply-Add) instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // FMA3 - Intel 3 operand Fused Multiply-Add instructions 16 //===----------------------------------------------------------------------===// 17 18 let Constraints = "$src1 = $dst" in { 19 multiclass fma3p_rm<bits<8> opc, string OpcodeStr, 20 PatFrag MemFrag128, PatFrag MemFrag256, 21 ValueType OpVT128, ValueType OpVT256, 22 bit IsRVariantCommutable = 0, bit IsMVariantCommutable = 0, 23 SDPatternOperator Op = null_frag> { 24 let usesCustomInserter = 1, isCommutable = IsRVariantCommutable in 25 def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst), 26 (ins VR128:$src1, VR128:$src2, VR128:$src3), 27 !strconcat(OpcodeStr, 28 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 29 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, 30 VR128:$src1, VR128:$src3)))]>; 31 32 let mayLoad = 1, isCommutable = IsMVariantCommutable in 33 def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst), 34 (ins VR128:$src1, VR128:$src2, f128mem:$src3), 35 !strconcat(OpcodeStr, 36 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 37 [(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1, 38 (MemFrag128 addr:$src3))))]>; 39 40 let usesCustomInserter = 1, isCommutable = IsRVariantCommutable in 41 def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst), 42 (ins VR256:$src1, VR256:$src2, VR256:$src3), 43 !strconcat(OpcodeStr, 44 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 45 [(set VR256:$dst, (OpVT256 (Op VR256:$src2, VR256:$src1, 46 VR256:$src3)))]>, VEX_L; 47 48 let mayLoad = 1, isCommutable = IsMVariantCommutable in 49 def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst), 50 (ins VR256:$src1, VR256:$src2, f256mem:$src3), 51 !strconcat(OpcodeStr, 52 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 53 [(set VR256:$dst, 54 (OpVT256 (Op VR256:$src2, VR256:$src1, 55 (MemFrag256 addr:$src3))))]>, VEX_L; 56 } 57 } // Constraints = "$src1 = $dst" 58 59 multiclass fma3p_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, 60 string OpcodeStr, string PackTy, 61 PatFrag MemFrag128, PatFrag MemFrag256, 62 SDNode Op, ValueType OpTy128, ValueType OpTy256> { 63 // For 213, both the register and memory variant are commutable. 64 // Indeed, the commutable operands are 1 and 2 and both live in registers 65 // for both variants. 66 defm r213 : fma3p_rm<opc213, 67 !strconcat(OpcodeStr, "213", PackTy), 68 MemFrag128, MemFrag256, OpTy128, OpTy256, 69 /* IsRVariantCommutable */ 1, 70 /* IsMVariantCommutable */ 1, 71 Op>; 72 let neverHasSideEffects = 1 in { 73 defm r132 : fma3p_rm<opc132, 74 !strconcat(OpcodeStr, "132", PackTy), 75 MemFrag128, MemFrag256, OpTy128, OpTy256>; 76 // For 231, only the register variant is commutable. 77 // For the memory variant the folded operand must be in 3. Thus, 78 // in that case, it cannot be swapped with 2. 79 defm r231 : fma3p_rm<opc231, 80 !strconcat(OpcodeStr, "231", PackTy), 81 MemFrag128, MemFrag256, OpTy128, OpTy256, 82 /* IsRVariantCommutable */ 1, 83 /* IsMVariantCommutable */ 0>; 84 } // neverHasSideEffects = 1 85 } 86 87 // Fused Multiply-Add 88 let ExeDomain = SSEPackedSingle in { 89 defm VFMADDPS : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "ps", loadv4f32, 90 loadv8f32, X86Fmadd, v4f32, v8f32>; 91 defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", loadv4f32, 92 loadv8f32, X86Fmsub, v4f32, v8f32>; 93 defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps", 94 loadv4f32, loadv8f32, X86Fmaddsub, 95 v4f32, v8f32>; 96 defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps", 97 loadv4f32, loadv8f32, X86Fmsubadd, 98 v4f32, v8f32>; 99 } 100 101 let ExeDomain = SSEPackedDouble in { 102 defm VFMADDPD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", loadv2f64, 103 loadv4f64, X86Fmadd, v2f64, v4f64>, VEX_W; 104 defm VFMSUBPD : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", loadv2f64, 105 loadv4f64, X86Fmsub, v2f64, v4f64>, VEX_W; 106 defm VFMADDSUBPD : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", 107 loadv2f64, loadv4f64, X86Fmaddsub, 108 v2f64, v4f64>, VEX_W; 109 defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", 110 loadv2f64, loadv4f64, X86Fmsubadd, 111 v2f64, v4f64>, VEX_W; 112 } 113 114 // Fused Negative Multiply-Add 115 let ExeDomain = SSEPackedSingle in { 116 defm VFNMADDPS : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "ps", loadv4f32, 117 loadv8f32, X86Fnmadd, v4f32, v8f32>; 118 defm VFNMSUBPS : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "ps", loadv4f32, 119 loadv8f32, X86Fnmsub, v4f32, v8f32>; 120 } 121 let ExeDomain = SSEPackedDouble in { 122 defm VFNMADDPD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", loadv2f64, 123 loadv4f64, X86Fnmadd, v2f64, v4f64>, VEX_W; 124 defm VFNMSUBPD : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", 125 loadv2f64, loadv4f64, X86Fnmsub, v2f64, 126 v4f64>, VEX_W; 127 } 128 129 let Constraints = "$src1 = $dst" in { 130 multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop, 131 RegisterClass RC, ValueType OpVT, PatFrag mem_frag, 132 bit IsRVariantCommutable = 0, bit IsMVariantCommutable = 0, 133 SDPatternOperator OpNode = null_frag> { 134 let usesCustomInserter = 1, isCommutable = IsRVariantCommutable in 135 def r : FMA3<opc, MRMSrcReg, (outs RC:$dst), 136 (ins RC:$src1, RC:$src2, RC:$src3), 137 !strconcat(OpcodeStr, 138 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 139 [(set RC:$dst, 140 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>; 141 142 let mayLoad = 1, isCommutable = IsMVariantCommutable in 143 def m : FMA3<opc, MRMSrcMem, (outs RC:$dst), 144 (ins RC:$src1, RC:$src2, x86memop:$src3), 145 !strconcat(OpcodeStr, 146 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 147 [(set RC:$dst, 148 (OpVT (OpNode RC:$src2, RC:$src1, 149 (mem_frag addr:$src3))))]>; 150 } 151 } // Constraints = "$src1 = $dst" 152 153 multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231, 154 string OpStr, string PackTy, string PT2, Intrinsic Int, 155 SDNode OpNode, RegisterClass RC, ValueType OpVT, 156 X86MemOperand x86memop, Operand memop, PatFrag mem_frag, 157 ComplexPattern mem_cpat> { 158 let neverHasSideEffects = 1 in { 159 defm r132 : fma3s_rm<opc132, !strconcat(OpStr, "132", PackTy), 160 x86memop, RC, OpVT, mem_frag>; 161 // See the other defm of r231 for the explanation regarding the 162 // commutable flags. 163 defm r231 : fma3s_rm<opc231, !strconcat(OpStr, "231", PackTy), 164 x86memop, RC, OpVT, mem_frag, 165 /* IsRVariantCommutable */ 1, 166 /* IsMVariantCommutable */ 0>; 167 } 168 169 // See the other defm of r213 for the explanation regarding the 170 // commutable flags. 171 defm r213 : fma3s_rm<opc213, !strconcat(OpStr, "213", PackTy), 172 x86memop, RC, OpVT, mem_frag, 173 /* IsRVariantCommutable */ 1, 174 /* IsMVariantCommutable */ 1, 175 OpNode>; 176 } 177 178 multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231, 179 string OpStr, Intrinsic IntF32, Intrinsic IntF64, 180 SDNode OpNode> { 181 defm SS : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", IntF32, OpNode, 182 FR32, f32, f32mem, ssmem, loadf32, sse_load_f32>; 183 defm SD : fma3s_forms<opc132, opc213, opc231, OpStr, "sd", "PD", IntF64, OpNode, 184 FR64, f64, f64mem, sdmem, loadf64, sse_load_f64>, VEX_W; 185 186 def : Pat<(IntF32 VR128:$src1, VR128:$src2, VR128:$src3), 187 (COPY_TO_REGCLASS 188 (!cast<Instruction>(NAME#"SSr213r") 189 (COPY_TO_REGCLASS $src2, FR32), 190 (COPY_TO_REGCLASS $src1, FR32), 191 (COPY_TO_REGCLASS $src3, FR32)), 192 VR128)>; 193 194 def : Pat<(IntF64 VR128:$src1, VR128:$src2, VR128:$src3), 195 (COPY_TO_REGCLASS 196 (!cast<Instruction>(NAME#"SDr213r") 197 (COPY_TO_REGCLASS $src2, FR64), 198 (COPY_TO_REGCLASS $src1, FR64), 199 (COPY_TO_REGCLASS $src3, FR64)), 200 VR128)>; 201 } 202 203 defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", int_x86_fma_vfmadd_ss, 204 int_x86_fma_vfmadd_sd, X86Fmadd>, VEX_LIG; 205 defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", int_x86_fma_vfmsub_ss, 206 int_x86_fma_vfmsub_sd, X86Fmsub>, VEX_LIG; 207 208 defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", int_x86_fma_vfnmadd_ss, 209 int_x86_fma_vfnmadd_sd, X86Fnmadd>, VEX_LIG; 210 defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", int_x86_fma_vfnmsub_ss, 211 int_x86_fma_vfnmsub_sd, X86Fnmsub>, VEX_LIG; 212 213 214 //===----------------------------------------------------------------------===// 215 // FMA4 - AMD 4 operand Fused Multiply-Add instructions 216 //===----------------------------------------------------------------------===// 217 218 219 multiclass fma4s<bits<8> opc, string OpcodeStr, RegisterClass RC, 220 X86MemOperand x86memop, ValueType OpVT, SDNode OpNode, 221 PatFrag mem_frag> { 222 let isCommutable = 1 in 223 def rr : FMA4<opc, MRMSrcReg, (outs RC:$dst), 224 (ins RC:$src1, RC:$src2, RC:$src3), 225 !strconcat(OpcodeStr, 226 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 227 [(set RC:$dst, 228 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, MemOp4; 229 def rm : FMA4<opc, MRMSrcMem, (outs RC:$dst), 230 (ins RC:$src1, RC:$src2, x86memop:$src3), 231 !strconcat(OpcodeStr, 232 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 233 [(set RC:$dst, (OpNode RC:$src1, RC:$src2, 234 (mem_frag addr:$src3)))]>, VEX_W, VEX_LIG, MemOp4; 235 def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst), 236 (ins RC:$src1, x86memop:$src2, RC:$src3), 237 !strconcat(OpcodeStr, 238 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 239 [(set RC:$dst, 240 (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3))]>, VEX_LIG; 241 // For disassembler 242 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in 243 def rr_REV : FMA4<opc, MRMSrcReg, (outs RC:$dst), 244 (ins RC:$src1, RC:$src2, RC:$src3), 245 !strconcat(OpcodeStr, 246 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, 247 VEX_LIG; 248 } 249 250 multiclass fma4s_int<bits<8> opc, string OpcodeStr, Operand memop, 251 ComplexPattern mem_cpat, Intrinsic Int> { 252 let isCodeGenOnly = 1 in { 253 let isCommutable = 1 in 254 def rr_Int : FMA4<opc, MRMSrcReg, (outs VR128:$dst), 255 (ins VR128:$src1, VR128:$src2, VR128:$src3), 256 !strconcat(OpcodeStr, 257 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 258 [(set VR128:$dst, 259 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_W, VEX_LIG, MemOp4; 260 def rm_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 261 (ins VR128:$src1, VR128:$src2, memop:$src3), 262 !strconcat(OpcodeStr, 263 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 264 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, 265 mem_cpat:$src3))]>, VEX_W, VEX_LIG, MemOp4; 266 def mr_Int : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 267 (ins VR128:$src1, memop:$src2, VR128:$src3), 268 !strconcat(OpcodeStr, 269 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 270 [(set VR128:$dst, 271 (Int VR128:$src1, mem_cpat:$src2, VR128:$src3))]>, VEX_LIG; 272 } // isCodeGenOnly = 1 273 } 274 275 multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode, 276 ValueType OpVT128, ValueType OpVT256, 277 PatFrag ld_frag128, PatFrag ld_frag256> { 278 let isCommutable = 1 in 279 def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst), 280 (ins VR128:$src1, VR128:$src2, VR128:$src3), 281 !strconcat(OpcodeStr, 282 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 283 [(set VR128:$dst, 284 (OpVT128 (OpNode VR128:$src1, VR128:$src2, VR128:$src3)))]>, 285 VEX_W, MemOp4; 286 def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 287 (ins VR128:$src1, VR128:$src2, f128mem:$src3), 288 !strconcat(OpcodeStr, 289 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 290 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2, 291 (ld_frag128 addr:$src3)))]>, VEX_W, MemOp4; 292 def mr : FMA4<opc, MRMSrcMem, (outs VR128:$dst), 293 (ins VR128:$src1, f128mem:$src2, VR128:$src3), 294 !strconcat(OpcodeStr, 295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 296 [(set VR128:$dst, 297 (OpNode VR128:$src1, (ld_frag128 addr:$src2), VR128:$src3))]>; 298 let isCommutable = 1 in 299 def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst), 300 (ins VR256:$src1, VR256:$src2, VR256:$src3), 301 !strconcat(OpcodeStr, 302 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 303 [(set VR256:$dst, 304 (OpVT256 (OpNode VR256:$src1, VR256:$src2, VR256:$src3)))]>, 305 VEX_W, MemOp4, VEX_L; 306 def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst), 307 (ins VR256:$src1, VR256:$src2, f256mem:$src3), 308 !strconcat(OpcodeStr, 309 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 310 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2, 311 (ld_frag256 addr:$src3)))]>, VEX_W, MemOp4, VEX_L; 312 def mrY : FMA4<opc, MRMSrcMem, (outs VR256:$dst), 313 (ins VR256:$src1, f256mem:$src2, VR256:$src3), 314 !strconcat(OpcodeStr, 315 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), 316 [(set VR256:$dst, (OpNode VR256:$src1, 317 (ld_frag256 addr:$src2), VR256:$src3))]>, VEX_L; 318 // For disassembler 319 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 320 def rr_REV : FMA4<opc, MRMSrcReg, (outs VR128:$dst), 321 (ins VR128:$src1, VR128:$src2, VR128:$src3), 322 !strconcat(OpcodeStr, 323 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>; 324 def rrY_REV : FMA4<opc, MRMSrcReg, (outs VR256:$dst), 325 (ins VR256:$src1, VR256:$src2, VR256:$src3), 326 !strconcat(OpcodeStr, 327 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, 328 VEX_L; 329 } // isCodeGenOnly = 1 330 } 331 332 defm VFMADDSS4 : fma4s<0x6A, "vfmaddss", FR32, f32mem, f32, X86Fmadd, loadf32>, 333 fma4s_int<0x6A, "vfmaddss", ssmem, sse_load_f32, 334 int_x86_fma_vfmadd_ss>; 335 defm VFMADDSD4 : fma4s<0x6B, "vfmaddsd", FR64, f64mem, f64, X86Fmadd, loadf64>, 336 fma4s_int<0x6B, "vfmaddsd", sdmem, sse_load_f64, 337 int_x86_fma_vfmadd_sd>; 338 defm VFMSUBSS4 : fma4s<0x6E, "vfmsubss", FR32, f32mem, f32, X86Fmsub, loadf32>, 339 fma4s_int<0x6E, "vfmsubss", ssmem, sse_load_f32, 340 int_x86_fma_vfmsub_ss>; 341 defm VFMSUBSD4 : fma4s<0x6F, "vfmsubsd", FR64, f64mem, f64, X86Fmsub, loadf64>, 342 fma4s_int<0x6F, "vfmsubsd", sdmem, sse_load_f64, 343 int_x86_fma_vfmsub_sd>; 344 defm VFNMADDSS4 : fma4s<0x7A, "vfnmaddss", FR32, f32mem, f32, 345 X86Fnmadd, loadf32>, 346 fma4s_int<0x7A, "vfnmaddss", ssmem, sse_load_f32, 347 int_x86_fma_vfnmadd_ss>; 348 defm VFNMADDSD4 : fma4s<0x7B, "vfnmaddsd", FR64, f64mem, f64, 349 X86Fnmadd, loadf64>, 350 fma4s_int<0x7B, "vfnmaddsd", sdmem, sse_load_f64, 351 int_x86_fma_vfnmadd_sd>; 352 defm VFNMSUBSS4 : fma4s<0x7E, "vfnmsubss", FR32, f32mem, f32, 353 X86Fnmsub, loadf32>, 354 fma4s_int<0x7E, "vfnmsubss", ssmem, sse_load_f32, 355 int_x86_fma_vfnmsub_ss>; 356 defm VFNMSUBSD4 : fma4s<0x7F, "vfnmsubsd", FR64, f64mem, f64, 357 X86Fnmsub, loadf64>, 358 fma4s_int<0x7F, "vfnmsubsd", sdmem, sse_load_f64, 359 int_x86_fma_vfnmsub_sd>; 360 361 let ExeDomain = SSEPackedSingle in { 362 defm VFMADDPS4 : fma4p<0x68, "vfmaddps", X86Fmadd, v4f32, v8f32, 363 loadv4f32, loadv8f32>; 364 defm VFMSUBPS4 : fma4p<0x6C, "vfmsubps", X86Fmsub, v4f32, v8f32, 365 loadv4f32, loadv8f32>; 366 defm VFNMADDPS4 : fma4p<0x78, "vfnmaddps", X86Fnmadd, v4f32, v8f32, 367 loadv4f32, loadv8f32>; 368 defm VFNMSUBPS4 : fma4p<0x7C, "vfnmsubps", X86Fnmsub, v4f32, v8f32, 369 loadv4f32, loadv8f32>; 370 defm VFMADDSUBPS4 : fma4p<0x5C, "vfmaddsubps", X86Fmaddsub, v4f32, v8f32, 371 loadv4f32, loadv8f32>; 372 defm VFMSUBADDPS4 : fma4p<0x5E, "vfmsubaddps", X86Fmsubadd, v4f32, v8f32, 373 loadv4f32, loadv8f32>; 374 } 375 376 let ExeDomain = SSEPackedDouble in { 377 defm VFMADDPD4 : fma4p<0x69, "vfmaddpd", X86Fmadd, v2f64, v4f64, 378 loadv2f64, loadv4f64>; 379 defm VFMSUBPD4 : fma4p<0x6D, "vfmsubpd", X86Fmsub, v2f64, v4f64, 380 loadv2f64, loadv4f64>; 381 defm VFNMADDPD4 : fma4p<0x79, "vfnmaddpd", X86Fnmadd, v2f64, v4f64, 382 loadv2f64, loadv4f64>; 383 defm VFNMSUBPD4 : fma4p<0x7D, "vfnmsubpd", X86Fnmsub, v2f64, v4f64, 384 loadv2f64, loadv4f64>; 385 defm VFMADDSUBPD4 : fma4p<0x5D, "vfmaddsubpd", X86Fmaddsub, v2f64, v4f64, 386 loadv2f64, loadv4f64>; 387 defm VFMSUBADDPD4 : fma4p<0x5F, "vfmsubaddpd", X86Fmsubadd, v2f64, v4f64, 388 loadv2f64, loadv4f64>; 389 } 390 391
