1 //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 instruction set, defining the instructions, and 11 // properties of the instructions which are needed for code generation, machine 12 // code emission, and analysis. 13 // 14 //===----------------------------------------------------------------------===// 15 16 //===----------------------------------------------------------------------===// 17 // X86 specific DAG Nodes. 18 // 19 20 def SDTIntShiftDOp: SDTypeProfile<1, 3, 21 [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, 22 SDTCisInt<0>, SDTCisInt<3>]>; 23 24 def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; 25 26 def SDTX86Cmps : SDTypeProfile<1, 3, [SDTCisFP<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 27 //def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; 28 29 def SDTX86Cmov : SDTypeProfile<1, 4, 30 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 31 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 32 33 // Unary and binary operator instructions that set EFLAGS as a side-effect. 34 def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 35 [SDTCisInt<0>, SDTCisVT<1, i32>]>; 36 37 def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 38 [SDTCisSameAs<0, 2>, 39 SDTCisSameAs<0, 3>, 40 SDTCisInt<0>, SDTCisVT<1, i32>]>; 41 42 // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 43 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 44 [SDTCisSameAs<0, 2>, 45 SDTCisSameAs<0, 3>, 46 SDTCisInt<0>, 47 SDTCisVT<1, i32>, 48 SDTCisVT<4, i32>]>; 49 // RES1, RES2, FLAGS = op LHS, RHS 50 def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 51 [SDTCisSameAs<0, 1>, 52 SDTCisSameAs<0, 2>, 53 SDTCisSameAs<0, 3>, 54 SDTCisInt<0>, SDTCisVT<1, i32>]>; 55 def SDTX86BrCond : SDTypeProfile<0, 3, 56 [SDTCisVT<0, OtherVT>, 57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 58 59 def SDTX86SetCC : SDTypeProfile<1, 2, 60 [SDTCisVT<0, i8>, 61 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 62 def SDTX86SetCC_C : SDTypeProfile<1, 2, 63 [SDTCisInt<0>, 64 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 65 66 def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 67 68 def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 69 70 def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 71 SDTCisVT<2, i8>]>; 72 def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73 74 def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, 75 SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; 76 def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; 77 78 def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 79 def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 80 SDTCisVT<1, i32>]>; 81 82 def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 83 84 def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 85 SDTCisVT<1, iPTR>, 86 SDTCisVT<2, iPTR>]>; 87 88 def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 89 SDTCisPtrTy<1>, 90 SDTCisVT<2, i32>, 91 SDTCisVT<3, i8>, 92 SDTCisVT<4, i32>]>; 93 94 def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 95 96 def SDTX86Void : SDTypeProfile<0, 0, []>; 97 98 def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 99 100 def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 101 102 def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 103 104 def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 105 106 def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 107 108 def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>; 109 110 def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 111 112 def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 113 114 def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 115 116 def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 117 [SDNPHasChain,SDNPSideEffect]>; 118 def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 119 [SDNPHasChain]>; 120 def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, 121 [SDNPHasChain]>; 122 def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, 123 [SDNPHasChain]>; 124 125 126 def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 127 def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 128 def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; 129 def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; 130 131 def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 132 def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 133 134 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 135 def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 136 [SDNPHasChain]>; 137 def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 138 def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 139 140 def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; 141 142 def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 143 [SDNPHasChain, SDNPSideEffect]>; 144 145 def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 146 [SDNPHasChain, SDNPSideEffect]>; 147 148 def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 149 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 150 SDNPMayLoad, SDNPMemOperand]>; 151 def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 152 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 153 SDNPMayLoad, SDNPMemOperand]>; 154 def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 155 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 156 SDNPMayLoad, SDNPMemOperand]>; 157 158 def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 159 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 160 161 def X86vastart_save_xmm_regs : 162 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 163 SDT_X86VASTART_SAVE_XMM_REGS, 164 [SDNPHasChain, SDNPVariadic]>; 165 def X86vaarg64 : 166 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 167 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 168 SDNPMemOperand]>; 169 def X86callseq_start : 170 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 171 [SDNPHasChain, SDNPOutGlue]>; 172 def X86callseq_end : 173 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 174 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 175 176 def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 177 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 178 SDNPVariadic]>; 179 180 def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 181 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 182 def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 183 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 184 SDNPMayLoad]>; 185 186 def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, 187 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 188 def X86rdtscp : SDNode<"X86ISD::RDTSCP_DAG", SDTX86Void, 189 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 190 def X86rdpmc : SDNode<"X86ISD::RDPMC_DAG", SDTX86Void, 191 [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; 192 193 def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 194 def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 195 196 def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 197 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 198 199 def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 201 202 def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 203 [SDNPHasChain]>; 204 205 def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 206 SDTypeProfile<1, 1, [SDTCisInt<0>, 207 SDTCisPtrTy<1>]>, 208 [SDNPHasChain, SDNPSideEffect]>; 209 def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 210 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 211 [SDNPHasChain, SDNPSideEffect]>; 212 213 def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 214 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 215 216 def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 217 [SDNPCommutative]>; 218 def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 219 def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 220 [SDNPCommutative]>; 221 def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 222 [SDNPCommutative]>; 223 def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 224 def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 225 226 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; 227 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; 228 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 229 [SDNPCommutative]>; 230 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 231 [SDNPCommutative]>; 232 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 233 [SDNPCommutative]>; 234 235 def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 236 237 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 238 239 def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, 240 [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; 241 242 def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 243 [SDNPHasChain]>; 244 245 def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 246 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 247 248 def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL, 249 [SDNPHasChain, SDNPOutGlue]>; 250 251 //===----------------------------------------------------------------------===// 252 // X86 Operand Definitions. 253 // 254 255 // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 256 // the index operand of an address, to conform to x86 encoding restrictions. 257 def ptr_rc_nosp : PointerLikeRegClass<1>; 258 259 // *mem - Operand definitions for the funky X86 addressing mode operands. 260 // 261 def X86MemAsmOperand : AsmOperandClass { 262 let Name = "Mem"; 263 } 264 def X86Mem8AsmOperand : AsmOperandClass { 265 let Name = "Mem8"; let RenderMethod = "addMemOperands"; 266 } 267 def X86Mem16AsmOperand : AsmOperandClass { 268 let Name = "Mem16"; let RenderMethod = "addMemOperands"; 269 } 270 def X86Mem32AsmOperand : AsmOperandClass { 271 let Name = "Mem32"; let RenderMethod = "addMemOperands"; 272 } 273 def X86Mem64AsmOperand : AsmOperandClass { 274 let Name = "Mem64"; let RenderMethod = "addMemOperands"; 275 } 276 def X86Mem80AsmOperand : AsmOperandClass { 277 let Name = "Mem80"; let RenderMethod = "addMemOperands"; 278 } 279 def X86Mem128AsmOperand : AsmOperandClass { 280 let Name = "Mem128"; let RenderMethod = "addMemOperands"; 281 } 282 def X86Mem256AsmOperand : AsmOperandClass { 283 let Name = "Mem256"; let RenderMethod = "addMemOperands"; 284 } 285 def X86Mem512AsmOperand : AsmOperandClass { 286 let Name = "Mem512"; let RenderMethod = "addMemOperands"; 287 } 288 289 // Gather mem operands 290 def X86MemVX32Operand : AsmOperandClass { 291 let Name = "MemVX32"; let RenderMethod = "addMemOperands"; 292 } 293 def X86MemVY32Operand : AsmOperandClass { 294 let Name = "MemVY32"; let RenderMethod = "addMemOperands"; 295 } 296 def X86MemVZ32Operand : AsmOperandClass { 297 let Name = "MemVZ32"; let RenderMethod = "addMemOperands"; 298 } 299 def X86MemVX64Operand : AsmOperandClass { 300 let Name = "MemVX64"; let RenderMethod = "addMemOperands"; 301 } 302 def X86MemVY64Operand : AsmOperandClass { 303 let Name = "MemVY64"; let RenderMethod = "addMemOperands"; 304 } 305 def X86MemVZ64Operand : AsmOperandClass { 306 let Name = "MemVZ64"; let RenderMethod = "addMemOperands"; 307 } 308 309 def X86AbsMemAsmOperand : AsmOperandClass { 310 let Name = "AbsMem"; 311 let SuperClasses = [X86MemAsmOperand]; 312 } 313 class X86MemOperand<string printMethod> : Operand<iPTR> { 314 let PrintMethod = printMethod; 315 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); 316 let ParserMatchClass = X86MemAsmOperand; 317 } 318 319 let OperandType = "OPERAND_MEMORY" in { 320 def opaque32mem : X86MemOperand<"printopaquemem">; 321 def opaque48mem : X86MemOperand<"printopaquemem">; 322 def opaque80mem : X86MemOperand<"printopaquemem">; 323 def opaque512mem : X86MemOperand<"printopaquemem">; 324 325 def i8mem : X86MemOperand<"printi8mem"> { 326 let ParserMatchClass = X86Mem8AsmOperand; } 327 def i16mem : X86MemOperand<"printi16mem"> { 328 let ParserMatchClass = X86Mem16AsmOperand; } 329 def i32mem : X86MemOperand<"printi32mem"> { 330 let ParserMatchClass = X86Mem32AsmOperand; } 331 def i64mem : X86MemOperand<"printi64mem"> { 332 let ParserMatchClass = X86Mem64AsmOperand; } 333 def i128mem : X86MemOperand<"printi128mem"> { 334 let ParserMatchClass = X86Mem128AsmOperand; } 335 def i256mem : X86MemOperand<"printi256mem"> { 336 let ParserMatchClass = X86Mem256AsmOperand; } 337 def i512mem : X86MemOperand<"printi512mem"> { 338 let ParserMatchClass = X86Mem512AsmOperand; } 339 def f32mem : X86MemOperand<"printf32mem"> { 340 let ParserMatchClass = X86Mem32AsmOperand; } 341 def f64mem : X86MemOperand<"printf64mem"> { 342 let ParserMatchClass = X86Mem64AsmOperand; } 343 def f80mem : X86MemOperand<"printf80mem"> { 344 let ParserMatchClass = X86Mem80AsmOperand; } 345 def f128mem : X86MemOperand<"printf128mem"> { 346 let ParserMatchClass = X86Mem128AsmOperand; } 347 def f256mem : X86MemOperand<"printf256mem">{ 348 let ParserMatchClass = X86Mem256AsmOperand; } 349 def f512mem : X86MemOperand<"printf512mem">{ 350 let ParserMatchClass = X86Mem512AsmOperand; } 351 def v512mem : Operand<iPTR> { 352 let PrintMethod = "printf512mem"; 353 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm); 354 let ParserMatchClass = X86Mem512AsmOperand; } 355 356 // Gather mem operands 357 def vx32mem : X86MemOperand<"printi32mem">{ 358 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); 359 let ParserMatchClass = X86MemVX32Operand; } 360 def vy32mem : X86MemOperand<"printi32mem">{ 361 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); 362 let ParserMatchClass = X86MemVY32Operand; } 363 def vx64mem : X86MemOperand<"printi64mem">{ 364 let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); 365 let ParserMatchClass = X86MemVX64Operand; } 366 def vy64mem : X86MemOperand<"printi64mem">{ 367 let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); 368 let ParserMatchClass = X86MemVY64Operand; } 369 def vy64xmem : X86MemOperand<"printi64mem">{ 370 let MIOperandInfo = (ops ptr_rc, i8imm, VR256X, i32imm, i8imm); 371 let ParserMatchClass = X86MemVY64Operand; } 372 def vz32mem : X86MemOperand<"printi32mem">{ 373 let MIOperandInfo = (ops ptr_rc, i16imm, VR512, i32imm, i8imm); 374 let ParserMatchClass = X86MemVZ32Operand; } 375 def vz64mem : X86MemOperand<"printi64mem">{ 376 let MIOperandInfo = (ops ptr_rc, i8imm, VR512, i32imm, i8imm); 377 let ParserMatchClass = X86MemVZ64Operand; } 378 } 379 380 // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of 381 // plain GR64, so that it doesn't potentially require a REX prefix. 382 def i8mem_NOREX : Operand<i64> { 383 let PrintMethod = "printi8mem"; 384 let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); 385 let ParserMatchClass = X86Mem8AsmOperand; 386 let OperandType = "OPERAND_MEMORY"; 387 } 388 389 // GPRs available for tailcall. 390 // It represents GR32_TC, GR64_TC or GR64_TCW64. 391 def ptr_rc_tailcall : PointerLikeRegClass<2>; 392 393 // Special i32mem for addresses of load folding tail calls. These are not 394 // allowed to use callee-saved registers since they must be scheduled 395 // after callee-saved register are popped. 396 def i32mem_TC : Operand<i32> { 397 let PrintMethod = "printi32mem"; 398 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 399 i32imm, i8imm); 400 let ParserMatchClass = X86Mem32AsmOperand; 401 let OperandType = "OPERAND_MEMORY"; 402 } 403 404 // Special i64mem for addresses of load folding tail calls. These are not 405 // allowed to use callee-saved registers since they must be scheduled 406 // after callee-saved register are popped. 407 def i64mem_TC : Operand<i64> { 408 let PrintMethod = "printi64mem"; 409 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 410 ptr_rc_tailcall, i32imm, i8imm); 411 let ParserMatchClass = X86Mem64AsmOperand; 412 let OperandType = "OPERAND_MEMORY"; 413 } 414 415 let OperandType = "OPERAND_PCREL", 416 ParserMatchClass = X86AbsMemAsmOperand, 417 PrintMethod = "printPCRelImm" in { 418 def i32imm_pcrel : Operand<i32>; 419 def i16imm_pcrel : Operand<i16>; 420 421 // Branch targets have OtherVT type and print as pc-relative values. 422 def brtarget : Operand<OtherVT>; 423 def brtarget8 : Operand<OtherVT>; 424 425 } 426 427 def X86SrcIdx8Operand : AsmOperandClass { 428 let Name = "SrcIdx8"; 429 let RenderMethod = "addSrcIdxOperands"; 430 let SuperClasses = [X86Mem8AsmOperand]; 431 } 432 def X86SrcIdx16Operand : AsmOperandClass { 433 let Name = "SrcIdx16"; 434 let RenderMethod = "addSrcIdxOperands"; 435 let SuperClasses = [X86Mem16AsmOperand]; 436 } 437 def X86SrcIdx32Operand : AsmOperandClass { 438 let Name = "SrcIdx32"; 439 let RenderMethod = "addSrcIdxOperands"; 440 let SuperClasses = [X86Mem32AsmOperand]; 441 } 442 def X86SrcIdx64Operand : AsmOperandClass { 443 let Name = "SrcIdx64"; 444 let RenderMethod = "addSrcIdxOperands"; 445 let SuperClasses = [X86Mem64AsmOperand]; 446 } 447 def X86DstIdx8Operand : AsmOperandClass { 448 let Name = "DstIdx8"; 449 let RenderMethod = "addDstIdxOperands"; 450 let SuperClasses = [X86Mem8AsmOperand]; 451 } 452 def X86DstIdx16Operand : AsmOperandClass { 453 let Name = "DstIdx16"; 454 let RenderMethod = "addDstIdxOperands"; 455 let SuperClasses = [X86Mem16AsmOperand]; 456 } 457 def X86DstIdx32Operand : AsmOperandClass { 458 let Name = "DstIdx32"; 459 let RenderMethod = "addDstIdxOperands"; 460 let SuperClasses = [X86Mem32AsmOperand]; 461 } 462 def X86DstIdx64Operand : AsmOperandClass { 463 let Name = "DstIdx64"; 464 let RenderMethod = "addDstIdxOperands"; 465 let SuperClasses = [X86Mem64AsmOperand]; 466 } 467 def X86MemOffs8AsmOperand : AsmOperandClass { 468 let Name = "MemOffs8"; 469 let RenderMethod = "addMemOffsOperands"; 470 let SuperClasses = [X86Mem8AsmOperand]; 471 } 472 def X86MemOffs16AsmOperand : AsmOperandClass { 473 let Name = "MemOffs16"; 474 let RenderMethod = "addMemOffsOperands"; 475 let SuperClasses = [X86Mem16AsmOperand]; 476 } 477 def X86MemOffs32AsmOperand : AsmOperandClass { 478 let Name = "MemOffs32"; 479 let RenderMethod = "addMemOffsOperands"; 480 let SuperClasses = [X86Mem32AsmOperand]; 481 } 482 def X86MemOffs64AsmOperand : AsmOperandClass { 483 let Name = "MemOffs64"; 484 let RenderMethod = "addMemOffsOperands"; 485 let SuperClasses = [X86Mem64AsmOperand]; 486 } 487 let OperandType = "OPERAND_MEMORY" in { 488 def srcidx8 : Operand<iPTR> { 489 let ParserMatchClass = X86SrcIdx8Operand; 490 let MIOperandInfo = (ops ptr_rc, i8imm); 491 let PrintMethod = "printSrcIdx8"; } 492 def srcidx16 : Operand<iPTR> { 493 let ParserMatchClass = X86SrcIdx16Operand; 494 let MIOperandInfo = (ops ptr_rc, i8imm); 495 let PrintMethod = "printSrcIdx16"; } 496 def srcidx32 : Operand<iPTR> { 497 let ParserMatchClass = X86SrcIdx32Operand; 498 let MIOperandInfo = (ops ptr_rc, i8imm); 499 let PrintMethod = "printSrcIdx32"; } 500 def srcidx64 : Operand<iPTR> { 501 let ParserMatchClass = X86SrcIdx64Operand; 502 let MIOperandInfo = (ops ptr_rc, i8imm); 503 let PrintMethod = "printSrcIdx64"; } 504 def dstidx8 : Operand<iPTR> { 505 let ParserMatchClass = X86DstIdx8Operand; 506 let MIOperandInfo = (ops ptr_rc); 507 let PrintMethod = "printDstIdx8"; } 508 def dstidx16 : Operand<iPTR> { 509 let ParserMatchClass = X86DstIdx16Operand; 510 let MIOperandInfo = (ops ptr_rc); 511 let PrintMethod = "printDstIdx16"; } 512 def dstidx32 : Operand<iPTR> { 513 let ParserMatchClass = X86DstIdx32Operand; 514 let MIOperandInfo = (ops ptr_rc); 515 let PrintMethod = "printDstIdx32"; } 516 def dstidx64 : Operand<iPTR> { 517 let ParserMatchClass = X86DstIdx64Operand; 518 let MIOperandInfo = (ops ptr_rc); 519 let PrintMethod = "printDstIdx64"; } 520 def offset8 : Operand<iPTR> { 521 let ParserMatchClass = X86MemOffs8AsmOperand; 522 let MIOperandInfo = (ops i64imm, i8imm); 523 let PrintMethod = "printMemOffs8"; } 524 def offset16 : Operand<iPTR> { 525 let ParserMatchClass = X86MemOffs16AsmOperand; 526 let MIOperandInfo = (ops i64imm, i8imm); 527 let PrintMethod = "printMemOffs16"; } 528 def offset32 : Operand<iPTR> { 529 let ParserMatchClass = X86MemOffs32AsmOperand; 530 let MIOperandInfo = (ops i64imm, i8imm); 531 let PrintMethod = "printMemOffs32"; } 532 def offset64 : Operand<iPTR> { 533 let ParserMatchClass = X86MemOffs64AsmOperand; 534 let MIOperandInfo = (ops i64imm, i8imm); 535 let PrintMethod = "printMemOffs64"; } 536 } 537 538 539 def SSECC : Operand<i8> { 540 let PrintMethod = "printSSECC"; 541 let OperandType = "OPERAND_IMMEDIATE"; 542 } 543 544 def AVXCC : Operand<i8> { 545 let PrintMethod = "printAVXCC"; 546 let OperandType = "OPERAND_IMMEDIATE"; 547 } 548 549 class ImmSExtAsmOperandClass : AsmOperandClass { 550 let SuperClasses = [ImmAsmOperand]; 551 let RenderMethod = "addImmOperands"; 552 } 553 554 class ImmZExtAsmOperandClass : AsmOperandClass { 555 let SuperClasses = [ImmAsmOperand]; 556 let RenderMethod = "addImmOperands"; 557 } 558 559 def X86GR32orGR64AsmOperand : AsmOperandClass { 560 let Name = "GR32orGR64"; 561 } 562 563 def GR32orGR64 : RegisterOperand<GR32> { 564 let ParserMatchClass = X86GR32orGR64AsmOperand; 565 } 566 567 def AVX512RC : Operand<i32> { 568 let PrintMethod = "printRoundingControl"; 569 let OperandType = "OPERAND_IMMEDIATE"; 570 } 571 // Sign-extended immediate classes. We don't need to define the full lattice 572 // here because there is no instruction with an ambiguity between ImmSExti64i32 573 // and ImmSExti32i8. 574 // 575 // The strange ranges come from the fact that the assembler always works with 576 // 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 577 // (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 578 579 // [0, 0x7FFFFFFF] | 580 // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 581 def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 582 let Name = "ImmSExti64i32"; 583 } 584 585 // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 586 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 587 def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 588 let Name = "ImmSExti16i8"; 589 let SuperClasses = [ImmSExti64i32AsmOperand]; 590 } 591 592 // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 593 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 594 def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 595 let Name = "ImmSExti32i8"; 596 } 597 598 // [0, 0x000000FF] 599 def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass { 600 let Name = "ImmZExtu32u8"; 601 } 602 603 604 // [0, 0x0000007F] | 605 // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 606 def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 607 let Name = "ImmSExti64i8"; 608 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 609 ImmSExti64i32AsmOperand]; 610 } 611 612 // A couple of more descriptive operand definitions. 613 // 16-bits but only 8 bits are significant. 614 def i16i8imm : Operand<i16> { 615 let ParserMatchClass = ImmSExti16i8AsmOperand; 616 let OperandType = "OPERAND_IMMEDIATE"; 617 } 618 // 32-bits but only 8 bits are significant. 619 def i32i8imm : Operand<i32> { 620 let ParserMatchClass = ImmSExti32i8AsmOperand; 621 let OperandType = "OPERAND_IMMEDIATE"; 622 } 623 // 32-bits but only 8 bits are significant, and those 8 bits are unsigned. 624 def u32u8imm : Operand<i32> { 625 let ParserMatchClass = ImmZExtu32u8AsmOperand; 626 let OperandType = "OPERAND_IMMEDIATE"; 627 } 628 629 // 64-bits but only 32 bits are significant. 630 def i64i32imm : Operand<i64> { 631 let ParserMatchClass = ImmSExti64i32AsmOperand; 632 let OperandType = "OPERAND_IMMEDIATE"; 633 } 634 635 // 64-bits but only 32 bits are significant, and those bits are treated as being 636 // pc relative. 637 def i64i32imm_pcrel : Operand<i64> { 638 let PrintMethod = "printPCRelImm"; 639 let ParserMatchClass = X86AbsMemAsmOperand; 640 let OperandType = "OPERAND_PCREL"; 641 } 642 643 // 64-bits but only 8 bits are significant. 644 def i64i8imm : Operand<i64> { 645 let ParserMatchClass = ImmSExti64i8AsmOperand; 646 let OperandType = "OPERAND_IMMEDIATE"; 647 } 648 649 def lea64_32mem : Operand<i32> { 650 let PrintMethod = "printi32mem"; 651 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 652 let ParserMatchClass = X86MemAsmOperand; 653 } 654 655 // Memory operands that use 64-bit pointers in both ILP32 and LP64. 656 def lea64mem : Operand<i64> { 657 let PrintMethod = "printi64mem"; 658 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, i8imm); 659 let ParserMatchClass = X86MemAsmOperand; 660 } 661 662 663 //===----------------------------------------------------------------------===// 664 // X86 Complex Pattern Definitions. 665 // 666 667 // Define X86 specific addressing mode. 668 def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; 669 def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", 670 [add, sub, mul, X86mul_imm, shl, or, frameindex], 671 []>; 672 // In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 673 def lea64_32addr : ComplexPattern<i32, 5, "SelectLEA64_32Addr", 674 [add, sub, mul, X86mul_imm, shl, or, 675 frameindex, X86WrapperRIP], 676 []>; 677 678 def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 679 [tglobaltlsaddr], []>; 680 681 def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", 682 [tglobaltlsaddr], []>; 683 684 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", 685 [add, sub, mul, X86mul_imm, shl, or, frameindex, 686 X86WrapperRIP], []>; 687 688 def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 689 [tglobaltlsaddr], []>; 690 691 def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", 692 [tglobaltlsaddr], []>; 693 694 //===----------------------------------------------------------------------===// 695 // X86 Instruction Predicate Definitions. 696 def HasCMov : Predicate<"Subtarget->hasCMov()">; 697 def NoCMov : Predicate<"!Subtarget->hasCMov()">; 698 699 def HasMMX : Predicate<"Subtarget->hasMMX()">; 700 def Has3DNow : Predicate<"Subtarget->has3DNow()">; 701 def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 702 def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 703 def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 704 def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 705 def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 706 def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 707 def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 708 def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 709 def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 710 def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 711 def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 712 def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 713 def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 714 def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 715 def HasAVX : Predicate<"Subtarget->hasAVX()">; 716 def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 717 def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 718 def HasAVX512 : Predicate<"Subtarget->hasAVX512()">, 719 AssemblerPredicate<"FeatureAVX512", "AVX-512 ISA">; 720 def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 721 def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 722 def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 723 def HasCDI : Predicate<"Subtarget->hasCDI()">; 724 def HasPFI : Predicate<"Subtarget->hasPFI()">; 725 def HasERI : Predicate<"Subtarget->hasERI()">; 726 727 def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 728 def HasAES : Predicate<"Subtarget->hasAES()">; 729 def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 730 def HasFMA : Predicate<"Subtarget->hasFMA()">; 731 def UseFMAOnAVX : Predicate<"Subtarget->hasFMA() && !Subtarget->hasAVX512()">; 732 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 733 def HasXOP : Predicate<"Subtarget->hasXOP()">; 734 def HasTBM : Predicate<"Subtarget->hasTBM()">; 735 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 736 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 737 def HasF16C : Predicate<"Subtarget->hasF16C()">; 738 def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 739 def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 740 def HasBMI : Predicate<"Subtarget->hasBMI()">; 741 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 742 def HasRTM : Predicate<"Subtarget->hasRTM()">; 743 def HasHLE : Predicate<"Subtarget->hasHLE()">; 744 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">; 745 def HasADX : Predicate<"Subtarget->hasADX()">; 746 def HasSHA : Predicate<"Subtarget->hasSHA()">; 747 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; 748 def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 749 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; 750 def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 751 def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 752 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 753 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 754 AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">; 755 def In64BitMode : Predicate<"Subtarget->is64Bit()">, 756 AssemblerPredicate<"Mode64Bit", "64-bit mode">; 757 def In16BitMode : Predicate<"Subtarget->is16Bit()">, 758 AssemblerPredicate<"Mode16Bit", "16-bit mode">; 759 def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 760 AssemblerPredicate<"!Mode16Bit", "Not 16-bit mode">; 761 def In32BitMode : Predicate<"Subtarget->is32Bit()">, 762 AssemblerPredicate<"Mode32Bit", "32-bit mode">; 763 def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 764 def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 765 def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 766 def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 767 def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 768 def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" 769 "TM.getCodeModel() != CodeModel::Kernel">; 770 def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 771 "TM.getCodeModel() == CodeModel::Kernel">; 772 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; 773 def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; 774 def OptForSize : Predicate<"OptForSize">; 775 def OptForSpeed : Predicate<"!OptForSize">; 776 def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; 777 def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; 778 def FavorMemIndirectCall : Predicate<"!Subtarget->callRegIndirect()">; 779 def NotSlowIncDec : Predicate<"!Subtarget->slowIncDec()">; 780 781 //===----------------------------------------------------------------------===// 782 // X86 Instruction Format Definitions. 783 // 784 785 include "X86InstrFormats.td" 786 787 //===----------------------------------------------------------------------===// 788 // Pattern fragments. 789 // 790 791 // X86 specific condition code. These correspond to CondCode in 792 // X86InstrInfo.h. They must be kept in synch. 793 def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE 794 def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC 795 def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 796 def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA 797 def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 798 def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE 799 def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL 800 def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE 801 def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG 802 def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ 803 def X86_COND_NO : PatLeaf<(i8 10)>; 804 def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 805 def X86_COND_NS : PatLeaf<(i8 12)>; 806 def X86_COND_O : PatLeaf<(i8 13)>; 807 def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE 808 def X86_COND_S : PatLeaf<(i8 15)>; 809 810 let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs. 811 def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; 812 def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; 813 def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; 814 } 815 816 def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; 817 818 819 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 820 // unsigned field. 821 def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; 822 823 def i64immZExt32SExt8 : ImmLeaf<i64, [{ 824 return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; 825 }]>; 826 827 // Helper fragments for loads. 828 // It's always safe to treat a anyext i16 load as a i32 load if the i16 is 829 // known to be 32-bit aligned or better. Ditto for i8 to i16. 830 def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 831 LoadSDNode *LD = cast<LoadSDNode>(N); 832 ISD::LoadExtType ExtType = LD->getExtensionType(); 833 if (ExtType == ISD::NON_EXTLOAD) 834 return true; 835 if (ExtType == ISD::EXTLOAD) 836 return LD->getAlignment() >= 2 && !LD->isVolatile(); 837 return false; 838 }]>; 839 840 def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ 841 LoadSDNode *LD = cast<LoadSDNode>(N); 842 ISD::LoadExtType ExtType = LD->getExtensionType(); 843 if (ExtType == ISD::EXTLOAD) 844 return LD->getAlignment() >= 2 && !LD->isVolatile(); 845 return false; 846 }]>; 847 848 def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 849 LoadSDNode *LD = cast<LoadSDNode>(N); 850 ISD::LoadExtType ExtType = LD->getExtensionType(); 851 if (ExtType == ISD::NON_EXTLOAD) 852 return true; 853 if (ExtType == ISD::EXTLOAD) 854 return LD->getAlignment() >= 4 && !LD->isVolatile(); 855 return false; 856 }]>; 857 858 def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; 859 def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 860 def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 861 def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 862 def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 863 864 def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 865 def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 866 def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 867 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 868 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 869 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 870 871 def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 872 def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 873 def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 874 def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 875 def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 876 def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 877 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 878 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 879 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 880 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 881 882 def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 883 def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 884 def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 885 def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 886 def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 887 def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 888 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 889 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 890 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 891 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; 892 893 894 // An 'and' node with a single use. 895 def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 896 return N->hasOneUse(); 897 }]>; 898 // An 'srl' node with a single use. 899 def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 900 return N->hasOneUse(); 901 }]>; 902 // An 'trunc' node with a single use. 903 def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 904 return N->hasOneUse(); 905 }]>; 906 907 //===----------------------------------------------------------------------===// 908 // Instruction list. 909 // 910 911 // Nop 912 let neverHasSideEffects = 1, SchedRW = [WriteZero] in { 913 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; 914 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 915 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16; 916 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 917 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32; 918 } 919 920 921 // Constructing a stack frame. 922 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 923 "enter\t$len, $lvl", [], IIC_ENTER>, Sched<[WriteMicrocoded]>; 924 925 let SchedRW = [WriteALU] in { 926 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in 927 def LEAVE : I<0xC9, RawFrm, 928 (outs), (ins), "leave", [], IIC_LEAVE>, 929 Requires<[Not64BitMode]>; 930 931 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in 932 def LEAVE64 : I<0xC9, RawFrm, 933 (outs), (ins), "leave", [], IIC_LEAVE>, 934 Requires<[In64BitMode]>; 935 } // SchedRW 936 937 //===----------------------------------------------------------------------===// 938 // Miscellaneous Instructions. 939 // 940 941 let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { 942 let mayLoad = 1, SchedRW = [WriteLoad] in { 943 def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 944 IIC_POP_REG16>, OpSize16; 945 def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 946 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 947 def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], 948 IIC_POP_REG>, OpSize16; 949 def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [], 950 IIC_POP_MEM>, OpSize16; 951 def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], 952 IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>; 953 def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [], 954 IIC_POP_MEM>, OpSize32, Requires<[Not64BitMode]>; 955 956 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, 957 OpSize16; 958 def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, 959 OpSize32, Requires<[Not64BitMode]>; 960 } // mayLoad, SchedRW 961 962 let mayStore = 1, SchedRW = [WriteStore] in { 963 def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 964 IIC_PUSH_REG>, OpSize16; 965 def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 966 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 967 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], 968 IIC_PUSH_REG>, OpSize16; 969 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], 970 IIC_PUSH_MEM>, OpSize16; 971 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], 972 IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>; 973 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], 974 IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>; 975 976 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 977 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 978 Requires<[Not64BitMode]>; 979 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 980 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 981 Requires<[Not64BitMode]>; 982 def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 983 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 984 Requires<[Not64BitMode]>; 985 def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 986 "push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 987 Requires<[Not64BitMode]>; 988 989 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, 990 OpSize16; 991 def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, 992 OpSize32, Requires<[Not64BitMode]>; 993 994 } // mayStore, SchedRW 995 } 996 997 let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in { 998 let mayLoad = 1, SchedRW = [WriteLoad] in { 999 def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1000 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1001 def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], 1002 IIC_POP_REG>, OpSize32, Requires<[In64BitMode]>; 1003 def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", [], 1004 IIC_POP_MEM>, OpSize32, Requires<[In64BitMode]>; 1005 } // mayLoad, SchedRW 1006 let mayStore = 1, SchedRW = [WriteStore] in { 1007 def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1008 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1009 def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], 1010 IIC_PUSH_REG>, OpSize32, Requires<[In64BitMode]>; 1011 def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], 1012 IIC_PUSH_MEM>, OpSize32, Requires<[In64BitMode]>; 1013 } // mayStore, SchedRW 1014 } 1015 1016 let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1, 1017 SchedRW = [WriteStore] in { 1018 def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1019 "push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>; 1020 def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1021 "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16, 1022 Requires<[In64BitMode]>; 1023 def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1024 "push{q}\t$imm", [], IIC_PUSH_IMM>, OpSize32, 1025 Requires<[In64BitMode]>; 1026 } 1027 1028 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in 1029 def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, 1030 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1031 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in 1032 def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, 1033 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1034 1035 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1036 mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in { 1037 def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>, 1038 OpSize32, Requires<[Not64BitMode]>; 1039 def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>, 1040 OpSize16, Requires<[Not64BitMode]>; 1041 } 1042 let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1043 mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in { 1044 def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>, 1045 OpSize32, Requires<[Not64BitMode]>; 1046 def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>, 1047 OpSize16, Requires<[Not64BitMode]>; 1048 } 1049 1050 let Constraints = "$src = $dst", SchedRW = [WriteALU] in { 1051 // GR32 = bswap GR32 1052 def BSWAP32r : I<0xC8, AddRegFrm, 1053 (outs GR32:$dst), (ins GR32:$src), 1054 "bswap{l}\t$dst", 1055 [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB; 1056 1057 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1058 "bswap{q}\t$dst", 1059 [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; 1060 } // Constraints = "$src = $dst", SchedRW 1061 1062 // Bit scan instructions. 1063 let Defs = [EFLAGS] in { 1064 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1065 "bsf{w}\t{$src, $dst|$dst, $src}", 1066 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], 1067 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1068 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1069 "bsf{w}\t{$src, $dst|$dst, $src}", 1070 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], 1071 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1072 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1073 "bsf{l}\t{$src, $dst|$dst, $src}", 1074 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], 1075 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1076 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1077 "bsf{l}\t{$src, $dst|$dst, $src}", 1078 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], 1079 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1080 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1081 "bsf{q}\t{$src, $dst|$dst, $src}", 1082 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], 1083 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1084 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1085 "bsf{q}\t{$src, $dst|$dst, $src}", 1086 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], 1087 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1088 1089 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1090 "bsr{w}\t{$src, $dst|$dst, $src}", 1091 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], 1092 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>; 1093 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1094 "bsr{w}\t{$src, $dst|$dst, $src}", 1095 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], 1096 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>; 1097 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1098 "bsr{l}\t{$src, $dst|$dst, $src}", 1099 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], 1100 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>; 1101 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1102 "bsr{l}\t{$src, $dst|$dst, $src}", 1103 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], 1104 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>; 1105 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1106 "bsr{q}\t{$src, $dst|$dst, $src}", 1107 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], 1108 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>; 1109 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1110 "bsr{q}\t{$src, $dst|$dst, $src}", 1111 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], 1112 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>; 1113 } // Defs = [EFLAGS] 1114 1115 let SchedRW = [WriteMicrocoded] in { 1116 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1117 let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { 1118 def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src), 1119 "movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1120 def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src), 1121 "movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16; 1122 def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src), 1123 "movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32; 1124 def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src), 1125 "movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>; 1126 } 1127 1128 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1129 let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in 1130 def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins), 1131 "stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>; 1132 let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in 1133 def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins), 1134 "stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16; 1135 let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in 1136 def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins), 1137 "stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32; 1138 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in 1139 def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins), 1140 "stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>; 1141 1142 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1143 let Defs = [EDI,EFLAGS], Uses = [AL,EDI,EFLAGS] in 1144 def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1145 "scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>; 1146 let Defs = [EDI,EFLAGS], Uses = [AX,EDI,EFLAGS] in 1147 def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1148 "scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16; 1149 let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,EFLAGS] in 1150 def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1151 "scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32; 1152 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,EFLAGS] in 1153 def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1154 "scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>; 1155 1156 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1157 let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,EFLAGS] in { 1158 def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1159 "cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1160 def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1161 "cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16; 1162 def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1163 "cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32; 1164 def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1165 "cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>; 1166 } 1167 } // SchedRW 1168 1169 //===----------------------------------------------------------------------===// 1170 // Move Instructions. 1171 // 1172 let SchedRW = [WriteMove] in { 1173 let neverHasSideEffects = 1 in { 1174 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1175 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1176 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1177 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1178 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1179 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1180 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1181 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1182 } 1183 1184 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1185 def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1186 "mov{b}\t{$src, $dst|$dst, $src}", 1187 [(set GR8:$dst, imm:$src)], IIC_MOV>; 1188 def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1189 "mov{w}\t{$src, $dst|$dst, $src}", 1190 [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16; 1191 def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1192 "mov{l}\t{$src, $dst|$dst, $src}", 1193 [(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32; 1194 def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1195 "mov{q}\t{$src, $dst|$dst, $src}", 1196 [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; 1197 } 1198 let isReMaterializable = 1 in { 1199 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1200 "movabs{q}\t{$src, $dst|$dst, $src}", 1201 [(set GR64:$dst, imm:$src)], IIC_MOV>; 1202 } 1203 1204 // Longer forms that use a ModR/M byte. Needed for disassembler 1205 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1206 def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1207 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1208 def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1209 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1210 def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1211 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1212 } 1213 } // SchedRW 1214 1215 let SchedRW = [WriteStore] in { 1216 def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1217 "mov{b}\t{$src, $dst|$dst, $src}", 1218 [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>; 1219 def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1220 "mov{w}\t{$src, $dst|$dst, $src}", 1221 [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16; 1222 def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1223 "mov{l}\t{$src, $dst|$dst, $src}", 1224 [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32; 1225 def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1226 "mov{q}\t{$src, $dst|$dst, $src}", 1227 [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>; 1228 } // SchedRW 1229 1230 let hasSideEffects = 0 in { 1231 1232 /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a 1233 /// 32-bit offset from the segment base. These are only valid in x86-32 mode. 1234 let SchedRW = [WriteALU] in { 1235 let mayLoad = 1 in { 1236 let Defs = [AL] in 1237 def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), 1238 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1239 Requires<[In32BitMode]>; 1240 let Defs = [AX] in 1241 def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), 1242 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1243 OpSize16, Requires<[In32BitMode]>; 1244 let Defs = [EAX] in 1245 def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), 1246 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1247 OpSize32, Requires<[In32BitMode]>; 1248 1249 let Defs = [AL] in 1250 def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), 1251 "mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>, 1252 AdSize, Requires<[In16BitMode]>; 1253 let Defs = [AX] in 1254 def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), 1255 "mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, 1256 OpSize16, AdSize, Requires<[In16BitMode]>; 1257 let Defs = [EAX] in 1258 def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), 1259 "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, 1260 AdSize, OpSize32, Requires<[In16BitMode]>; 1261 } 1262 let mayStore = 1 in { 1263 let Uses = [AL] in 1264 def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), 1265 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, 1266 Requires<[In32BitMode]>; 1267 let Uses = [AX] in 1268 def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), 1269 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1270 OpSize16, Requires<[In32BitMode]>; 1271 let Uses = [EAX] in 1272 def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), 1273 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1274 OpSize32, Requires<[In32BitMode]>; 1275 1276 let Uses = [AL] in 1277 def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), 1278 "mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>, 1279 AdSize, Requires<[In16BitMode]>; 1280 let Uses = [AX] in 1281 def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), 1282 "mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, 1283 OpSize16, AdSize, Requires<[In16BitMode]>; 1284 let Uses = [EAX] in 1285 def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), 1286 "mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>, 1287 OpSize32, AdSize, Requires<[In16BitMode]>; 1288 } 1289 } 1290 1291 // These forms all have full 64-bit absolute addresses in their instructions 1292 // and use the movabs mnemonic to indicate this specific form. 1293 let mayLoad = 1 in { 1294 let Defs = [AL] in 1295 def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src), 1296 "movabs{b}\t{$src, %al|al, $src}", []>, 1297 Requires<[In64BitMode]>; 1298 let Defs = [AX] in 1299 def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src), 1300 "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16, 1301 Requires<[In64BitMode]>; 1302 let Defs = [EAX] in 1303 def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src), 1304 "movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32, 1305 Requires<[In64BitMode]>; 1306 let Defs = [RAX] in 1307 def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src), 1308 "movabs{q}\t{$src, %rax|rax, $src}", []>, 1309 Requires<[In64BitMode]>; 1310 } 1311 1312 let mayStore = 1 in { 1313 let Uses = [AL] in 1314 def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins), 1315 "movabs{b}\t{%al, $dst|$dst, al}", []>, 1316 Requires<[In64BitMode]>; 1317 let Uses = [AX] in 1318 def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins), 1319 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16, 1320 Requires<[In64BitMode]>; 1321 let Uses = [EAX] in 1322 def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins), 1323 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32, 1324 Requires<[In64BitMode]>; 1325 let Uses = [RAX] in 1326 def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins), 1327 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, 1328 Requires<[In64BitMode]>; 1329 } 1330 } // hasSideEffects = 0 1331 1332 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1333 SchedRW = [WriteMove] in { 1334 def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1335 "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1336 def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1337 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16; 1338 def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1339 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32; 1340 def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1341 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; 1342 } 1343 1344 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1345 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1346 "mov{b}\t{$src, $dst|$dst, $src}", 1347 [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; 1348 def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1349 "mov{w}\t{$src, $dst|$dst, $src}", 1350 [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16; 1351 def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1352 "mov{l}\t{$src, $dst|$dst, $src}", 1353 [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; 1354 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1355 "mov{q}\t{$src, $dst|$dst, $src}", 1356 [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; 1357 } 1358 1359 let SchedRW = [WriteStore] in { 1360 def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1361 "mov{b}\t{$src, $dst|$dst, $src}", 1362 [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; 1363 def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1364 "mov{w}\t{$src, $dst|$dst, $src}", 1365 [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; 1366 def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1367 "mov{l}\t{$src, $dst|$dst, $src}", 1368 [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; 1369 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1370 "mov{q}\t{$src, $dst|$dst, $src}", 1371 [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; 1372 } // SchedRW 1373 1374 // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1375 // that they can be used for copying and storing h registers, which can't be 1376 // encoded when a REX prefix is present. 1377 let isCodeGenOnly = 1 in { 1378 let neverHasSideEffects = 1 in 1379 def MOV8rr_NOREX : I<0x88, MRMDestReg, 1380 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1381 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>, 1382 Sched<[WriteMove]>; 1383 let mayStore = 1, neverHasSideEffects = 1 in 1384 def MOV8mr_NOREX : I<0x88, MRMDestMem, 1385 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1386 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1387 IIC_MOV_MEM>, Sched<[WriteStore]>; 1388 let mayLoad = 1, neverHasSideEffects = 1, 1389 canFoldAsLoad = 1, isReMaterializable = 1 in 1390 def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1391 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1392 "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], 1393 IIC_MOV_MEM>, Sched<[WriteLoad]>; 1394 } 1395 1396 1397 // Condition code ops, incl. set if equal/not equal/... 1398 let SchedRW = [WriteALU] in { 1399 let Defs = [EFLAGS], Uses = [AH] in 1400 def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", 1401 [(set EFLAGS, (X86sahf AH))], IIC_AHF>; 1402 let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in 1403 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], 1404 IIC_AHF>; // AH = flags 1405 } // SchedRW 1406 1407 //===----------------------------------------------------------------------===// 1408 // Bit tests instructions: BT, BTS, BTR, BTC. 1409 1410 let Defs = [EFLAGS] in { 1411 let SchedRW = [WriteALU] in { 1412 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1413 "bt{w}\t{$src2, $src1|$src1, $src2}", 1414 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, 1415 OpSize16, TB; 1416 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1417 "bt{l}\t{$src2, $src1|$src1, $src2}", 1418 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, 1419 OpSize32, TB; 1420 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1421 "bt{q}\t{$src2, $src1|$src1, $src2}", 1422 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB; 1423 } // SchedRW 1424 1425 // Unlike with the register+register form, the memory+register form of the 1426 // bt instruction does not ignore the high bits of the index. From ISel's 1427 // perspective, this is pretty bizarre. Make these instructions disassembly 1428 // only for now. 1429 1430 let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in { 1431 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1432 "bt{w}\t{$src2, $src1|$src1, $src2}", 1433 // [(X86bt (loadi16 addr:$src1), GR16:$src2), 1434 // (implicit EFLAGS)] 1435 [], IIC_BT_MR 1436 >, OpSize16, TB, Requires<[FastBTMem]>; 1437 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1438 "bt{l}\t{$src2, $src1|$src1, $src2}", 1439 // [(X86bt (loadi32 addr:$src1), GR32:$src2), 1440 // (implicit EFLAGS)] 1441 [], IIC_BT_MR 1442 >, OpSize32, TB, Requires<[FastBTMem]>; 1443 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1444 "bt{q}\t{$src2, $src1|$src1, $src2}", 1445 // [(X86bt (loadi64 addr:$src1), GR64:$src2), 1446 // (implicit EFLAGS)] 1447 [], IIC_BT_MR 1448 >, TB; 1449 } 1450 1451 let SchedRW = [WriteALU] in { 1452 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1453 "bt{w}\t{$src2, $src1|$src1, $src2}", 1454 [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], 1455 IIC_BT_RI>, OpSize16, TB; 1456 def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1457 "bt{l}\t{$src2, $src1|$src1, $src2}", 1458 [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], 1459 IIC_BT_RI>, OpSize32, TB; 1460 def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1461 "bt{q}\t{$src2, $src1|$src1, $src2}", 1462 [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], 1463 IIC_BT_RI>, TB; 1464 } // SchedRW 1465 1466 // Note that these instructions don't need FastBTMem because that 1467 // only applies when the other operand is in a register. When it's 1468 // an immediate, bt is still fast. 1469 let SchedRW = [WriteALU] in { 1470 def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1471 "bt{w}\t{$src2, $src1|$src1, $src2}", 1472 [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) 1473 ], IIC_BT_MI>, OpSize16, TB; 1474 def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1475 "bt{l}\t{$src2, $src1|$src1, $src2}", 1476 [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) 1477 ], IIC_BT_MI>, OpSize32, TB; 1478 def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1479 "bt{q}\t{$src2, $src1|$src1, $src2}", 1480 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1481 i64immSExt8:$src2))], IIC_BT_MI>, TB; 1482 } // SchedRW 1483 1484 let hasSideEffects = 0 in { 1485 let SchedRW = [WriteALU] in { 1486 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1487 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1488 OpSize16, TB; 1489 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1490 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1491 OpSize32, TB; 1492 def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1493 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1494 } // SchedRW 1495 1496 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1497 def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1498 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1499 OpSize16, TB; 1500 def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1501 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1502 OpSize32, TB; 1503 def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1504 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1505 } 1506 1507 let SchedRW = [WriteALU] in { 1508 def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1509 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1510 OpSize16, TB; 1511 def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1512 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1513 OpSize32, TB; 1514 def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1515 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1516 } // SchedRW 1517 1518 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1519 def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1520 "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1521 OpSize16, TB; 1522 def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1523 "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1524 OpSize32, TB; 1525 def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1526 "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1527 } 1528 1529 let SchedRW = [WriteALU] in { 1530 def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1531 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1532 OpSize16, TB; 1533 def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1534 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1535 OpSize32, TB; 1536 def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1537 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1538 } // SchedRW 1539 1540 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1541 def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1542 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1543 OpSize16, TB; 1544 def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1545 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1546 OpSize32, TB; 1547 def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1548 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1549 } 1550 1551 let SchedRW = [WriteALU] in { 1552 def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1553 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1554 OpSize16, TB; 1555 def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1556 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1557 OpSize32, TB; 1558 def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1559 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1560 } // SchedRW 1561 1562 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1563 def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1564 "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1565 OpSize16, TB; 1566 def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1567 "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1568 OpSize32, TB; 1569 def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1570 "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1571 } 1572 1573 let SchedRW = [WriteALU] in { 1574 def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1575 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1576 OpSize16, TB; 1577 def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1578 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, 1579 OpSize32, TB; 1580 def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1581 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; 1582 } // SchedRW 1583 1584 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1585 def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1586 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1587 OpSize16, TB; 1588 def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1589 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, 1590 OpSize32, TB; 1591 def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1592 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; 1593 } 1594 1595 let SchedRW = [WriteALU] in { 1596 def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), 1597 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1598 OpSize16, TB; 1599 def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), 1600 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, 1601 OpSize32, TB; 1602 def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), 1603 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; 1604 } // SchedRW 1605 1606 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1607 def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), 1608 "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1609 OpSize16, TB; 1610 def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), 1611 "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, 1612 OpSize32, TB; 1613 def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), 1614 "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; 1615 } 1616 } // hasSideEffects = 0 1617 } // Defs = [EFLAGS] 1618 1619 1620 //===----------------------------------------------------------------------===// 1621 // Atomic support 1622 // 1623 1624 // Atomic swap. These are just normal xchg instructions. But since a memory 1625 // operand is referenced, the atomicity is ensured. 1626 multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag, 1627 InstrItinClass itin> { 1628 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 1629 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 1630 (ins GR8:$val, i8mem:$ptr), 1631 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 1632 [(set 1633 GR8:$dst, 1634 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))], 1635 itin>; 1636 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 1637 (ins GR16:$val, i16mem:$ptr), 1638 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 1639 [(set 1640 GR16:$dst, 1641 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))], 1642 itin>, OpSize16; 1643 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 1644 (ins GR32:$val, i32mem:$ptr), 1645 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 1646 [(set 1647 GR32:$dst, 1648 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))], 1649 itin>, OpSize32; 1650 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 1651 (ins GR64:$val, i64mem:$ptr), 1652 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 1653 [(set 1654 GR64:$dst, 1655 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))], 1656 itin>; 1657 } 1658 } 1659 1660 defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap", IIC_XCHG_MEM>; 1661 1662 // Swap between registers. 1663 let SchedRW = [WriteALU] in { 1664 let Constraints = "$val = $dst" in { 1665 def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), 1666 "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1667 def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), 1668 "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1669 OpSize16; 1670 def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), 1671 "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, 1672 OpSize32; 1673 def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), 1674 "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; 1675 } 1676 1677 // Swap between EAX and other registers. 1678 let Uses = [AX], Defs = [AX] in 1679 def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), 1680 "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16; 1681 let Uses = [EAX], Defs = [EAX] in 1682 def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), 1683 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1684 OpSize32, Requires<[Not64BitMode]>; 1685 let Uses = [EAX], Defs = [EAX] in 1686 // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. 1687 // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. 1688 def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), 1689 "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, 1690 OpSize32, Requires<[In64BitMode]>; 1691 let Uses = [RAX], Defs = [RAX] in 1692 def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), 1693 "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; 1694 } // SchedRW 1695 1696 let SchedRW = [WriteALU] in { 1697 def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1698 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1699 def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1700 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1701 OpSize16; 1702 def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1703 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, 1704 OpSize32; 1705 def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1706 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; 1707 } // SchedRW 1708 1709 let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in { 1710 def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1711 "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1712 def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1713 "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1714 OpSize16; 1715 def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1716 "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, 1717 OpSize32; 1718 def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1719 "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; 1720 1721 } 1722 1723 let SchedRW = [WriteALU] in { 1724 def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 1725 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1726 IIC_CMPXCHG_REG8>, TB; 1727 def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1728 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1729 IIC_CMPXCHG_REG>, TB, OpSize16; 1730 def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1731 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1732 IIC_CMPXCHG_REG>, TB, OpSize32; 1733 def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1734 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1735 IIC_CMPXCHG_REG>, TB; 1736 } // SchedRW 1737 1738 let SchedRW = [WriteALULd, WriteRMW] in { 1739 let mayLoad = 1, mayStore = 1 in { 1740 def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 1741 "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], 1742 IIC_CMPXCHG_MEM8>, TB; 1743 def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1744 "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], 1745 IIC_CMPXCHG_MEM>, TB, OpSize16; 1746 def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1747 "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], 1748 IIC_CMPXCHG_MEM>, TB, OpSize32; 1749 def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1750 "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], 1751 IIC_CMPXCHG_MEM>, TB; 1752 } 1753 1754 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 1755 def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 1756 "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; 1757 1758 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 1759 def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 1760 "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, 1761 TB, Requires<[HasCmpxchg16b]>; 1762 } // SchedRW 1763 1764 1765 // Lock instruction prefix 1766 def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; 1767 1768 // Rex64 instruction prefix 1769 def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>, 1770 Requires<[In64BitMode]>; 1771 1772 // Data16 instruction prefix 1773 def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; 1774 1775 // Repeat string operation instruction prefixes 1776 // These uses the DF flag in the EFLAGS register to inc or dec ECX 1777 let Defs = [ECX], Uses = [ECX,EFLAGS] in { 1778 // Repeat (used with INS, OUTS, MOVS, LODS and STOS) 1779 def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; 1780 // Repeat while not equal (used with CMPS and SCAS) 1781 def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; 1782 } 1783 1784 1785 // String manipulation instructions 1786 let SchedRW = [WriteMicrocoded] in { 1787 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1788 let Defs = [AL,ESI], Uses = [ESI,EFLAGS] in 1789 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 1790 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>; 1791 let Defs = [AX,ESI], Uses = [ESI,EFLAGS] in 1792 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 1793 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16; 1794 let Defs = [EAX,ESI], Uses = [ESI,EFLAGS] in 1795 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 1796 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32; 1797 let Defs = [RAX,ESI], Uses = [ESI,EFLAGS] in 1798 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 1799 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>; 1800 } 1801 1802 let SchedRW = [WriteSystem] in { 1803 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1804 let Defs = [ESI], Uses = [DX,ESI,EFLAGS] in { 1805 def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 1806 "outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>; 1807 def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 1808 "outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16; 1809 def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 1810 "outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32; 1811 } 1812 1813 // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI 1814 let Defs = [EDI], Uses = [DX,EDI,EFLAGS] in { 1815 def INSB : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins), 1816 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>; 1817 def INSW : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins), 1818 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16; 1819 def INSL : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins), 1820 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32; 1821 } 1822 } 1823 1824 // Flag instructions 1825 let SchedRW = [WriteALU] in { 1826 def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; 1827 def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; 1828 def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; 1829 def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; 1830 def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; 1831 def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; 1832 def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; 1833 1834 def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; 1835 } 1836 1837 // Table lookup instructions 1838 def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>, 1839 Sched<[WriteLoad]>; 1840 1841 let SchedRW = [WriteMicrocoded] in { 1842 // ASCII Adjust After Addition 1843 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1844 def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, 1845 Requires<[Not64BitMode]>; 1846 1847 // ASCII Adjust AX Before Division 1848 // sets AL, AH and EFLAGS and uses AL and AH 1849 def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 1850 "aad\t$src", [], IIC_AAD>, Requires<[Not64BitMode]>; 1851 1852 // ASCII Adjust AX After Multiply 1853 // sets AL, AH and EFLAGS and uses AL 1854 def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 1855 "aam\t$src", [], IIC_AAM>, Requires<[Not64BitMode]>; 1856 1857 // ASCII Adjust AL After Subtraction - sets 1858 // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS 1859 def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, 1860 Requires<[Not64BitMode]>; 1861 1862 // Decimal Adjust AL after Addition 1863 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1864 def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, 1865 Requires<[Not64BitMode]>; 1866 1867 // Decimal Adjust AL after Subtraction 1868 // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS 1869 def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, 1870 Requires<[Not64BitMode]>; 1871 } // SchedRW 1872 1873 let SchedRW = [WriteSystem] in { 1874 // Check Array Index Against Bounds 1875 def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1876 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16, 1877 Requires<[Not64BitMode]>; 1878 def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1879 "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32, 1880 Requires<[Not64BitMode]>; 1881 1882 // Adjust RPL Field of Segment Selector 1883 def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1884 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, 1885 Requires<[Not64BitMode]>; 1886 def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1887 "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, 1888 Requires<[Not64BitMode]>; 1889 } // SchedRW 1890 1891 //===----------------------------------------------------------------------===// 1892 // MOVBE Instructions 1893 // 1894 let Predicates = [HasMOVBE] in { 1895 let SchedRW = [WriteALULd] in { 1896 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1897 "movbe{w}\t{$src, $dst|$dst, $src}", 1898 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, 1899 OpSize16, T8PS; 1900 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1901 "movbe{l}\t{$src, $dst|$dst, $src}", 1902 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, 1903 OpSize32, T8PS; 1904 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1905 "movbe{q}\t{$src, $dst|$dst, $src}", 1906 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, 1907 T8PS; 1908 } 1909 let SchedRW = [WriteStore] in { 1910 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1911 "movbe{w}\t{$src, $dst|$dst, $src}", 1912 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, 1913 OpSize16, T8PS; 1914 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1915 "movbe{l}\t{$src, $dst|$dst, $src}", 1916 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, 1917 OpSize32, T8PS; 1918 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1919 "movbe{q}\t{$src, $dst|$dst, $src}", 1920 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, 1921 T8PS; 1922 } 1923 } 1924 1925 //===----------------------------------------------------------------------===// 1926 // RDRAND Instruction 1927 // 1928 let Predicates = [HasRDRAND], Defs = [EFLAGS] in { 1929 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 1930 "rdrand{w}\t$dst", 1931 [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB; 1932 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 1933 "rdrand{l}\t$dst", 1934 [(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB; 1935 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 1936 "rdrand{q}\t$dst", 1937 [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB; 1938 } 1939 1940 //===----------------------------------------------------------------------===// 1941 // RDSEED Instruction 1942 // 1943 let Predicates = [HasRDSEED], Defs = [EFLAGS] in { 1944 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), 1945 "rdseed{w}\t$dst", 1946 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB; 1947 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), 1948 "rdseed{l}\t$dst", 1949 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB; 1950 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), 1951 "rdseed{q}\t$dst", 1952 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB; 1953 } 1954 1955 //===----------------------------------------------------------------------===// 1956 // LZCNT Instruction 1957 // 1958 let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 1959 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1960 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1961 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, 1962 OpSize16; 1963 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1964 "lzcnt{w}\t{$src, $dst|$dst, $src}", 1965 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 1966 (implicit EFLAGS)]>, XS, OpSize16; 1967 1968 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1969 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1970 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS, 1971 OpSize32; 1972 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1973 "lzcnt{l}\t{$src, $dst|$dst, $src}", 1974 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 1975 (implicit EFLAGS)]>, XS, OpSize32; 1976 1977 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1978 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1979 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 1980 XS; 1981 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1982 "lzcnt{q}\t{$src, $dst|$dst, $src}", 1983 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 1984 (implicit EFLAGS)]>, XS; 1985 } 1986 1987 let Predicates = [HasLZCNT] in { 1988 def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E), 1989 (X86cmp GR16:$src, (i16 0))), 1990 (LZCNT16rr GR16:$src)>; 1991 def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E), 1992 (X86cmp GR32:$src, (i32 0))), 1993 (LZCNT32rr GR32:$src)>; 1994 def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E), 1995 (X86cmp GR64:$src, (i64 0))), 1996 (LZCNT64rr GR64:$src)>; 1997 def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E), 1998 (X86cmp GR16:$src, (i16 0))), 1999 (LZCNT16rr GR16:$src)>; 2000 def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E), 2001 (X86cmp GR32:$src, (i32 0))), 2002 (LZCNT32rr GR32:$src)>; 2003 def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E), 2004 (X86cmp GR64:$src, (i64 0))), 2005 (LZCNT64rr GR64:$src)>; 2006 2007 def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E), 2008 (X86cmp (loadi16 addr:$src), (i16 0))), 2009 (LZCNT16rm addr:$src)>; 2010 def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E), 2011 (X86cmp (loadi32 addr:$src), (i32 0))), 2012 (LZCNT32rm addr:$src)>; 2013 def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E), 2014 (X86cmp (loadi64 addr:$src), (i64 0))), 2015 (LZCNT64rm addr:$src)>; 2016 def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E), 2017 (X86cmp (loadi16 addr:$src), (i16 0))), 2018 (LZCNT16rm addr:$src)>; 2019 def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E), 2020 (X86cmp (loadi32 addr:$src), (i32 0))), 2021 (LZCNT32rm addr:$src)>; 2022 def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E), 2023 (X86cmp (loadi64 addr:$src), (i64 0))), 2024 (LZCNT64rm addr:$src)>; 2025 } 2026 2027 //===----------------------------------------------------------------------===// 2028 // BMI Instructions 2029 // 2030 let Predicates = [HasBMI], Defs = [EFLAGS] in { 2031 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2032 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2033 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, 2034 OpSize16; 2035 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2036 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2037 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2038 (implicit EFLAGS)]>, XS, OpSize16; 2039 2040 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2041 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2042 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS, 2043 OpSize32; 2044 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2045 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2046 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2047 (implicit EFLAGS)]>, XS, OpSize32; 2048 2049 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2050 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2051 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2052 XS; 2053 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2054 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2055 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2056 (implicit EFLAGS)]>, XS; 2057 } 2058 2059 multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2060 RegisterClass RC, X86MemOperand x86memop> { 2061 let hasSideEffects = 0 in { 2062 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2063 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2064 []>, T8PS, VEX_4V; 2065 let mayLoad = 1 in 2066 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2067 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), 2068 []>, T8PS, VEX_4V; 2069 } 2070 } 2071 2072 let Predicates = [HasBMI], Defs = [EFLAGS] in { 2073 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem>; 2074 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem>, VEX_W; 2075 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem>; 2076 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem>, VEX_W; 2077 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem>; 2078 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem>, VEX_W; 2079 } 2080 2081 //===----------------------------------------------------------------------===// 2082 // Pattern fragments to auto generate BMI instructions. 2083 //===----------------------------------------------------------------------===// 2084 2085 let Predicates = [HasBMI] in { 2086 // FIXME: patterns for the load versions are not implemented 2087 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2088 (BLSR32rr GR32:$src)>; 2089 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2090 (BLSR64rr GR64:$src)>; 2091 2092 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2093 (BLSMSK32rr GR32:$src)>; 2094 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2095 (BLSMSK64rr GR64:$src)>; 2096 2097 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2098 (BLSI32rr GR32:$src)>; 2099 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2100 (BLSI64rr GR64:$src)>; 2101 } 2102 2103 let Predicates = [HasBMI] in { 2104 def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E), 2105 (X86cmp GR16:$src, (i16 0))), 2106 (TZCNT16rr GR16:$src)>; 2107 def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E), 2108 (X86cmp GR32:$src, (i32 0))), 2109 (TZCNT32rr GR32:$src)>; 2110 def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E), 2111 (X86cmp GR64:$src, (i64 0))), 2112 (TZCNT64rr GR64:$src)>; 2113 def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E), 2114 (X86cmp GR16:$src, (i16 0))), 2115 (TZCNT16rr GR16:$src)>; 2116 def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E), 2117 (X86cmp GR32:$src, (i32 0))), 2118 (TZCNT32rr GR32:$src)>; 2119 def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E), 2120 (X86cmp GR64:$src, (i64 0))), 2121 (TZCNT64rr GR64:$src)>; 2122 2123 def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E), 2124 (X86cmp (loadi16 addr:$src), (i16 0))), 2125 (TZCNT16rm addr:$src)>; 2126 def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E), 2127 (X86cmp (loadi32 addr:$src), (i32 0))), 2128 (TZCNT32rm addr:$src)>; 2129 def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E), 2130 (X86cmp (loadi64 addr:$src), (i64 0))), 2131 (TZCNT64rm addr:$src)>; 2132 def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E), 2133 (X86cmp (loadi16 addr:$src), (i16 0))), 2134 (TZCNT16rm addr:$src)>; 2135 def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E), 2136 (X86cmp (loadi32 addr:$src), (i32 0))), 2137 (TZCNT32rm addr:$src)>; 2138 def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E), 2139 (X86cmp (loadi64 addr:$src), (i64 0))), 2140 (TZCNT64rm addr:$src)>; 2141 } 2142 2143 2144 multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2145 X86MemOperand x86memop, Intrinsic Int, 2146 PatFrag ld_frag> { 2147 def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2148 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2149 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2150 T8PS, VEX_4VOp3; 2151 def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2152 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2153 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2154 (implicit EFLAGS)]>, T8PS, VEX_4VOp3; 2155 } 2156 2157 let Predicates = [HasBMI], Defs = [EFLAGS] in { 2158 defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, 2159 int_x86_bmi_bextr_32, loadi32>; 2160 defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, 2161 int_x86_bmi_bextr_64, loadi64>, VEX_W; 2162 } 2163 2164 let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2165 defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2166 int_x86_bmi_bzhi_32, loadi32>; 2167 defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2168 int_x86_bmi_bzhi_64, loadi64>, VEX_W; 2169 } 2170 2171 2172 def CountTrailingOnes : SDNodeXForm<imm, [{ 2173 // Count the trailing ones in the immediate. 2174 return getI8Imm(CountTrailingOnes_64(N->getZExtValue())); 2175 }]>; 2176 2177 def BZHIMask : ImmLeaf<i64, [{ 2178 return isMask_64(Imm) && (CountTrailingOnes_64(Imm) > 32); 2179 }]>; 2180 2181 let Predicates = [HasBMI2] in { 2182 def : Pat<(and GR64:$src, BZHIMask:$mask), 2183 (BZHI64rr GR64:$src, 2184 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2185 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2186 2187 def : Pat<(and GR32:$src, (add (shl 1, GR8:$lz), -1)), 2188 (BZHI32rr GR32:$src, 2189 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2190 2191 def : Pat<(and (loadi32 addr:$src), (add (shl 1, GR8:$lz), -1)), 2192 (BZHI32rm addr:$src, 2193 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2194 2195 def : Pat<(and GR64:$src, (add (shl 1, GR8:$lz), -1)), 2196 (BZHI64rr GR64:$src, 2197 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2198 2199 def : Pat<(and (loadi64 addr:$src), (add (shl 1, GR8:$lz), -1)), 2200 (BZHI64rm addr:$src, 2201 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR8:$lz, sub_8bit))>; 2202 } // HasBMI2 2203 2204 let Predicates = [HasBMI] in { 2205 def : Pat<(X86bextr GR32:$src1, GR32:$src2), 2206 (BEXTR32rr GR32:$src1, GR32:$src2)>; 2207 def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2), 2208 (BEXTR32rm addr:$src1, GR32:$src2)>; 2209 def : Pat<(X86bextr GR64:$src1, GR64:$src2), 2210 (BEXTR64rr GR64:$src1, GR64:$src2)>; 2211 def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2), 2212 (BEXTR64rm addr:$src1, GR64:$src2)>; 2213 } // HasBMI 2214 2215 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2216 X86MemOperand x86memop, Intrinsic Int, 2217 PatFrag ld_frag> { 2218 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2219 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2220 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, 2221 VEX_4V; 2222 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2223 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2224 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; 2225 } 2226 2227 let Predicates = [HasBMI2] in { 2228 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2229 int_x86_bmi_pdep_32, loadi32>, T8XD; 2230 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2231 int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; 2232 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2233 int_x86_bmi_pext_32, loadi32>, T8XS; 2234 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2235 int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; 2236 } 2237 2238 //===----------------------------------------------------------------------===// 2239 // TBM Instructions 2240 // 2241 let Predicates = [HasTBM], Defs = [EFLAGS] in { 2242 2243 multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr, 2244 X86MemOperand x86memop, PatFrag ld_frag, 2245 Intrinsic Int, Operand immtype, 2246 SDPatternOperator immoperator> { 2247 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2248 !strconcat(OpcodeStr, 2249 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2250 [(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>, 2251 XOP, XOPA; 2252 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2253 (ins x86memop:$src1, immtype:$cntl), 2254 !strconcat(OpcodeStr, 2255 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2256 [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>, 2257 XOP, XOPA; 2258 } 2259 2260 defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr", i32mem, loadi32, 2261 int_x86_tbm_bextri_u32, i32imm, imm>; 2262 let ImmT = Imm32S in 2263 defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr", i64mem, loadi64, 2264 int_x86_tbm_bextri_u64, i64i32imm, 2265 i64immSExt32>, VEX_W; 2266 2267 multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2268 RegisterClass RC, string OpcodeStr, 2269 X86MemOperand x86memop, PatFrag ld_frag> { 2270 let hasSideEffects = 0 in { 2271 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2272 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2273 []>, XOP_4V, XOP9; 2274 let mayLoad = 1 in 2275 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2276 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), 2277 []>, XOP_4V, XOP9; 2278 } 2279 } 2280 2281 multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2282 Format FormReg, Format FormMem> { 2283 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr, i32mem, 2284 loadi32>; 2285 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr, i64mem, 2286 loadi64>, VEX_W; 2287 } 2288 2289 defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>; 2290 defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>; 2291 defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>; 2292 defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>; 2293 defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>; 2294 defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>; 2295 defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>; 2296 defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>; 2297 defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>; 2298 } // HasTBM, EFLAGS 2299 2300 //===----------------------------------------------------------------------===// 2301 // Pattern fragments to auto generate TBM instructions. 2302 //===----------------------------------------------------------------------===// 2303 2304 let Predicates = [HasTBM] in { 2305 def : Pat<(X86bextr GR32:$src1, (i32 imm:$src2)), 2306 (BEXTRI32ri GR32:$src1, imm:$src2)>; 2307 def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)), 2308 (BEXTRI32mi addr:$src1, imm:$src2)>; 2309 def : Pat<(X86bextr GR64:$src1, i64immSExt32:$src2), 2310 (BEXTRI64ri GR64:$src1, i64immSExt32:$src2)>; 2311 def : Pat<(X86bextr (loadi64 addr:$src1), i64immSExt32:$src2), 2312 (BEXTRI64mi addr:$src1, i64immSExt32:$src2)>; 2313 2314 // FIXME: patterns for the load versions are not implemented 2315 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2316 (BLCFILL32rr GR32:$src)>; 2317 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2318 (BLCFILL64rr GR64:$src)>; 2319 2320 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2321 (BLCI32rr GR32:$src)>; 2322 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2323 (BLCI64rr GR64:$src)>; 2324 2325 // Extra patterns because opt can optimize the above patterns to this. 2326 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2327 (BLCI32rr GR32:$src)>; 2328 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2329 (BLCI64rr GR64:$src)>; 2330 2331 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2332 (BLCIC32rr GR32:$src)>; 2333 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2334 (BLCIC64rr GR64:$src)>; 2335 2336 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2337 (BLCMSK32rr GR32:$src)>; 2338 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2339 (BLCMSK64rr GR64:$src)>; 2340 2341 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2342 (BLCS32rr GR32:$src)>; 2343 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2344 (BLCS64rr GR64:$src)>; 2345 2346 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2347 (BLSFILL32rr GR32:$src)>; 2348 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2349 (BLSFILL64rr GR64:$src)>; 2350 2351 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2352 (BLSIC32rr GR32:$src)>; 2353 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2354 (BLSIC64rr GR64:$src)>; 2355 2356 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2357 (T1MSKC32rr GR32:$src)>; 2358 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2359 (T1MSKC64rr GR64:$src)>; 2360 2361 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2362 (TZMSK32rr GR32:$src)>; 2363 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2364 (TZMSK64rr GR64:$src)>; 2365 } // HasTBM 2366 2367 //===----------------------------------------------------------------------===// 2368 // Subsystems. 2369 //===----------------------------------------------------------------------===// 2370 2371 include "X86InstrArithmetic.td" 2372 include "X86InstrCMovSetCC.td" 2373 include "X86InstrExtension.td" 2374 include "X86InstrControl.td" 2375 include "X86InstrShiftRotate.td" 2376 2377 // X87 Floating Point Stack. 2378 include "X86InstrFPStack.td" 2379 2380 // SIMD support (SSE, MMX and AVX) 2381 include "X86InstrFragmentsSIMD.td" 2382 2383 // FMA - Fused Multiply-Add support (requires FMA) 2384 include "X86InstrFMA.td" 2385 2386 // XOP 2387 include "X86InstrXOP.td" 2388 2389 // SSE, MMX and 3DNow! vector support. 2390 include "X86InstrSSE.td" 2391 include "X86InstrAVX512.td" 2392 include "X86InstrMMX.td" 2393 include "X86Instr3DNow.td" 2394 2395 include "X86InstrVMX.td" 2396 include "X86InstrSVM.td" 2397 2398 include "X86InstrTSX.td" 2399 2400 // System instructions. 2401 include "X86InstrSystem.td" 2402 2403 // Compiler Pseudo Instructions and Pat Patterns 2404 include "X86InstrCompiler.td" 2405 2406 //===----------------------------------------------------------------------===// 2407 // Assembler Mnemonic Aliases 2408 //===----------------------------------------------------------------------===// 2409 2410 def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 2411 def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 2412 def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 2413 2414 def : MnemonicAlias<"cbw", "cbtw", "att">; 2415 def : MnemonicAlias<"cwde", "cwtl", "att">; 2416 def : MnemonicAlias<"cwd", "cwtd", "att">; 2417 def : MnemonicAlias<"cdq", "cltd", "att">; 2418 def : MnemonicAlias<"cdqe", "cltq", "att">; 2419 def : MnemonicAlias<"cqo", "cqto", "att">; 2420 2421 // In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 2422 def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 2423 def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 2424 2425 def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 2426 def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 2427 2428 def : MnemonicAlias<"loopz", "loope", "att">; 2429 def : MnemonicAlias<"loopnz", "loopne", "att">; 2430 2431 def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 2432 def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 2433 def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 2434 def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 2435 def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 2436 def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 2437 def : MnemonicAlias<"popfd", "popfl", "att">; 2438 2439 // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 2440 // all modes. However: "push (addr)" and "push $42" should default to 2441 // pushl/pushq depending on the current mode. Similar for "pop %bx" 2442 def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 2443 def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 2444 def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 2445 def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 2446 def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 2447 def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 2448 def : MnemonicAlias<"pushfd", "pushfl", "att">; 2449 2450 def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 2451 def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 2452 def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 2453 def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 2454 def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 2455 def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 2456 2457 def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 2458 def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 2459 def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 2460 def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 2461 2462 def : MnemonicAlias<"repe", "rep", "att">; 2463 def : MnemonicAlias<"repz", "rep", "att">; 2464 def : MnemonicAlias<"repnz", "repne", "att">; 2465 2466 def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 2467 def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 2468 def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 2469 2470 def : MnemonicAlias<"salb", "shlb", "att">; 2471 def : MnemonicAlias<"salw", "shlw", "att">; 2472 def : MnemonicAlias<"sall", "shll", "att">; 2473 def : MnemonicAlias<"salq", "shlq", "att">; 2474 2475 def : MnemonicAlias<"smovb", "movsb", "att">; 2476 def : MnemonicAlias<"smovw", "movsw", "att">; 2477 def : MnemonicAlias<"smovl", "movsl", "att">; 2478 def : MnemonicAlias<"smovq", "movsq", "att">; 2479 2480 def : MnemonicAlias<"ud2a", "ud2", "att">; 2481 def : MnemonicAlias<"verrw", "verr", "att">; 2482 2483 // System instruction aliases. 2484 def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 2485 def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 2486 def : MnemonicAlias<"sysret", "sysretl", "att">; 2487 def : MnemonicAlias<"sysexit", "sysexitl", "att">; 2488 2489 def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 2490 def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 2491 def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 2492 def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 2493 def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 2494 def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 2495 def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 2496 def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 2497 def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 2498 def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 2499 def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 2500 def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 2501 2502 2503 // Floating point stack aliases. 2504 def : MnemonicAlias<"fcmovz", "fcmove", "att">; 2505 def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 2506 def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 2507 def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 2508 def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 2509 def : MnemonicAlias<"fcomip", "fcompi", "att">; 2510 def : MnemonicAlias<"fildq", "fildll", "att">; 2511 def : MnemonicAlias<"fistpq", "fistpll", "att">; 2512 def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 2513 def : MnemonicAlias<"fldcww", "fldcw", "att">; 2514 def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 2515 def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 2516 def : MnemonicAlias<"fucomip", "fucompi", "att">; 2517 def : MnemonicAlias<"fwait", "wait", "att">; 2518 2519 2520 class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 2521 string VariantName> 2522 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 2523 !strconcat(Prefix, NewCond, Suffix), VariantName>; 2524 2525 /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 2526 /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 2527 /// example "setz" -> "sete". 2528 multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 2529 string V = ""> { 2530 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 2531 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 2532 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 2533 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 2534 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 2535 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 2536 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 2537 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 2538 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 2539 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 2540 2541 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 2542 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 2543 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 2544 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 2545 } 2546 2547 // Aliases for set<CC> 2548 defm : IntegerCondCodeMnemonicAlias<"set", "">; 2549 // Aliases for j<CC> 2550 defm : IntegerCondCodeMnemonicAlias<"j", "">; 2551 // Aliases for cmov<CC>{w,l,q} 2552 defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 2553 defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 2554 defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 2555 // No size suffix for intel-style asm. 2556 defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 2557 2558 2559 //===----------------------------------------------------------------------===// 2560 // Assembler Instruction Aliases 2561 //===----------------------------------------------------------------------===// 2562 2563 // aad/aam default to base 10 if no operand is specified. 2564 def : InstAlias<"aad", (AAD8i8 10)>; 2565 def : InstAlias<"aam", (AAM8i8 10)>; 2566 2567 // Disambiguate the mem/imm form of bt-without-a-suffix as btl. 2568 // Likewise for btc/btr/bts. 2569 def : InstAlias<"bt {$imm, $mem|$mem, $imm}", 2570 (BT32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2571 def : InstAlias<"btc {$imm, $mem|$mem, $imm}", 2572 (BTC32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2573 def : InstAlias<"btr {$imm, $mem|$mem, $imm}", 2574 (BTR32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2575 def : InstAlias<"bts {$imm, $mem|$mem, $imm}", 2576 (BTS32mi8 i32mem:$mem, i32i8imm:$imm), 0>; 2577 2578 // clr aliases. 2579 def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 2580 def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 2581 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 2582 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 2583 2584 // lods aliases. Accept the destination being omitted because it's implicit 2585 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2586 // in the destination. 2587 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>; 2588 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>; 2589 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>; 2590 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2591 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 2592 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 2593 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 2594 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 2595 2596 // stos aliases. Accept the source being omitted because it's implicit in 2597 // the mnemonic, or the mnemonic suffix being omitted because it's implicit 2598 // in the source. 2599 def : InstAlias<"stosb $dst", (STOSB dstidx8:$dst), 0>; 2600 def : InstAlias<"stosw $dst", (STOSW dstidx16:$dst), 0>; 2601 def : InstAlias<"stos{l|d} $dst", (STOSL dstidx32:$dst), 0>; 2602 def : InstAlias<"stosq $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2603 def : InstAlias<"stos {%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 2604 def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 2605 def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 2606 def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2607 2608 // scas aliases. Accept the destination being omitted because it's implicit 2609 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit 2610 // in the destination. 2611 def : InstAlias<"scasb $dst", (SCASB dstidx8:$dst), 0>; 2612 def : InstAlias<"scasw $dst", (SCASW dstidx16:$dst), 0>; 2613 def : InstAlias<"scas{l|d} $dst", (SCASL dstidx32:$dst), 0>; 2614 def : InstAlias<"scasq $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2615 def : InstAlias<"scas {$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 2616 def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 2617 def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 2618 def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 2619 2620 // div and idiv aliases for explicit A register. 2621 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 2622 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 2623 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 2624 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 2625 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 2626 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 2627 def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 2628 def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 2629 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 2630 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 2631 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 2632 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 2633 def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 2634 def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 2635 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 2636 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 2637 2638 2639 2640 // Various unary fpstack operations default to operating on on ST1. 2641 // For example, "fxch" -> "fxch %st(1)" 2642 def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 2643 def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 2644 def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 2645 def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 2646 def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 2647 def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 2648 def : InstAlias<"fxch", (XCH_F ST1), 0>; 2649 def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 2650 def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 2651 def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 2652 def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 2653 def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 2654 def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 2655 def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 2656 def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 2657 2658 // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 2659 // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 2660 // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 2661 // gas. 2662 multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 2663 def : InstAlias<!strconcat(Mnemonic, "\t{$op, %st(0)|st(0), $op}"), 2664 (Inst RST:$op), EmitAlias>; 2665 def : InstAlias<!strconcat(Mnemonic, "\t{%st(0), %st(0)|st(0), st(0)}"), 2666 (Inst ST0), EmitAlias>; 2667 } 2668 2669 defm : FpUnaryAlias<"fadd", ADD_FST0r>; 2670 defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 2671 defm : FpUnaryAlias<"fsub", SUB_FST0r>; 2672 defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0>; 2673 defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; 2674 defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0>; 2675 defm : FpUnaryAlias<"fmul", MUL_FST0r>; 2676 defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; 2677 defm : FpUnaryAlias<"fdiv", DIV_FST0r>; 2678 defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0>; 2679 defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; 2680 defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0>; 2681 defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 2682 defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 2683 defm : FpUnaryAlias<"fcompi", COM_FIPr>; 2684 defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; 2685 2686 2687 // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they 2688 // commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 2689 // solely because gas supports it. 2690 def : InstAlias<"faddp\t{%st(0), $op|$op, st(0)}", (ADD_FPrST0 RST:$op), 0>; 2691 def : InstAlias<"fmulp\t{%st(0), $op|$op, st(0)}", (MUL_FPrST0 RST:$op)>; 2692 def : InstAlias<"fsub{|r}p\t{%st(0), $op|$op, st(0)}", (SUBR_FPrST0 RST:$op)>; 2693 def : InstAlias<"fsub{r|}p\t{%st(0), $op|$op, st(0)}", (SUB_FPrST0 RST:$op)>; 2694 def : InstAlias<"fdiv{|r}p\t{%st(0), $op|$op, st(0)}", (DIVR_FPrST0 RST:$op)>; 2695 def : InstAlias<"fdiv{r|}p\t{%st(0), $op|$op, st(0)}", (DIV_FPrST0 RST:$op)>; 2696 2697 // We accept "fnstsw %eax" even though it only writes %ax. 2698 def : InstAlias<"fnstsw\t{%eax|eax}", (FNSTSW16r)>; 2699 def : InstAlias<"fnstsw\t{%al|al}" , (FNSTSW16r)>; 2700 def : InstAlias<"fnstsw" , (FNSTSW16r)>; 2701 2702 // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 2703 // this is compatible with what GAS does. 2704 def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2705 def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[Not16BitMode]>; 2706 def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2707 def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst), 0>, Requires<[Not16BitMode]>; 2708 def : InstAlias<"lcall $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2709 def : InstAlias<"ljmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 2710 def : InstAlias<"lcall *$dst", (FARCALL16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2711 def : InstAlias<"ljmp *$dst", (FARJMP16m opaque32mem:$dst), 0>, Requires<[In16BitMode]>; 2712 2713 def : InstAlias<"call *$dst", (CALL64m i16mem:$dst), 0>, Requires<[In64BitMode]>; 2714 def : InstAlias<"jmp *$dst", (JMP64m i16mem:$dst), 0>, Requires<[In64BitMode]>; 2715 def : InstAlias<"call *$dst", (CALL32m i16mem:$dst), 0>, Requires<[In32BitMode]>; 2716 def : InstAlias<"jmp *$dst", (JMP32m i16mem:$dst), 0>, Requires<[In32BitMode]>; 2717 def : InstAlias<"call *$dst", (CALL16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2718 def : InstAlias<"jmp *$dst", (JMP16m i16mem:$dst), 0>, Requires<[In16BitMode]>; 2719 2720 2721 // "imul <imm>, B" is an alias for "imul <imm>, B, B". 2722 def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>; 2723 def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>; 2724 def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>; 2725 def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>; 2726 def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; 2727 def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; 2728 2729 // inb %dx -> inb %al, %dx 2730 def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 2731 def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 2732 def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 2733 def : InstAlias<"inb\t$port", (IN8ri i8imm:$port), 0>; 2734 def : InstAlias<"inw\t$port", (IN16ri i8imm:$port), 0>; 2735 def : InstAlias<"inl\t$port", (IN32ri i8imm:$port), 0>; 2736 2737 2738 // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 2739 def : InstAlias<"call $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2740 def : InstAlias<"jmp $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 2741 def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2742 def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not16BitMode]>; 2743 def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; 2744 def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; 2745 def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; 2746 def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; 2747 2748 // Force mov without a suffix with a segment and mem to prefer the 'l' form of 2749 // the move. All segment/mem forms are equivalent, this has the shortest 2750 // encoding. 2751 def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem), 0>; 2752 def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg), 0>; 2753 2754 // Match 'movq <largeimm>, <reg>' as an alias for movabsq. 2755 def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 2756 2757 // Match 'movq GR64, MMX' as an alias for movd. 2758 def : InstAlias<"movq $src, $dst", 2759 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 2760 def : InstAlias<"movq $src, $dst", 2761 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 2762 2763 // movsx aliases 2764 def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; 2765 def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; 2766 def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; 2767 def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; 2768 def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; 2769 def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; 2770 def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; 2771 2772 // movzx aliases 2773 def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; 2774 def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; 2775 def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; 2776 def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; 2777 def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; 2778 def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; 2779 // Note: No GR32->GR64 movzx form. 2780 2781 // outb %dx -> outb %al, %dx 2782 def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 2783 def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 2784 def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 2785 def : InstAlias<"outb\t$port", (OUT8ir i8imm:$port), 0>; 2786 def : InstAlias<"outw\t$port", (OUT16ir i8imm:$port), 0>; 2787 def : InstAlias<"outl\t$port", (OUT32ir i8imm:$port), 0>; 2788 2789 // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 2790 // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 2791 // errors, since its encoding is the most compact. 2792 def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 2793 2794 // shld/shrd op,op -> shld op, op, CL 2795 def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 2796 def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 2797 def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 2798 def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 2799 def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 2800 def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 2801 2802 def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 2803 def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 2804 def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 2805 def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 2806 def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 2807 def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 2808 2809 /* FIXME: This is disabled because the asm matcher is currently incapable of 2810 * matching a fixed immediate like $1. 2811 // "shl X, $1" is an alias for "shl X". 2812 multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 2813 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2814 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 2815 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2816 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 2817 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2818 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 2819 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2820 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 2821 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 2822 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 2823 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 2824 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 2825 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 2826 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 2827 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 2828 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 2829 } 2830 2831 defm : ShiftRotateByOneAlias<"rcl", "RCL">; 2832 defm : ShiftRotateByOneAlias<"rcr", "RCR">; 2833 defm : ShiftRotateByOneAlias<"rol", "ROL">; 2834 defm : ShiftRotateByOneAlias<"ror", "ROR">; 2835 FIXME */ 2836 2837 // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 2838 def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", 2839 (TEST8rm GR8 :$val, i8mem :$mem), 0>; 2840 def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", 2841 (TEST16rm GR16:$val, i16mem:$mem), 0>; 2842 def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", 2843 (TEST32rm GR32:$val, i32mem:$mem), 0>; 2844 def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", 2845 (TEST64rm GR64:$val, i64mem:$mem), 0>; 2846 2847 // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 2848 def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 2849 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 2850 def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 2851 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 2852 def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 2853 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 2854 def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 2855 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 2856 2857 // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 2858 def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 2859 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2860 (XCHG32ar GR32:$src), 0>, Requires<[Not64BitMode]>; 2861 def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", 2862 (XCHG32ar64 GR32_NOAX:$src), 0>, Requires<[In64BitMode]>; 2863 def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 2864
