1 //===-- X86InstrMMX.td - Describe the MMX Instruction Set --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the X86 MMX instruction set, defining the instructions, 11 // and properties of the instructions which are needed for code generation, 12 // machine code emission, and analysis. 13 // 14 // All instructions that use MMX should be in this file, even if they also use 15 // SSE. 16 // 17 //===----------------------------------------------------------------------===// 18 19 //===----------------------------------------------------------------------===// 20 // MMX Multiclasses 21 //===----------------------------------------------------------------------===// 22 23 let Sched = WriteVecALU in { 24 def MMX_INTALU_ITINS : OpndItins< 25 IIC_MMX_ALU_RR, IIC_MMX_ALU_RM 26 >; 27 28 def MMX_INTALUQ_ITINS : OpndItins< 29 IIC_MMX_ALUQ_RR, IIC_MMX_ALUQ_RM 30 >; 31 32 def MMX_PHADDSUBW : OpndItins< 33 IIC_MMX_PHADDSUBW_RR, IIC_MMX_PHADDSUBW_RM 34 >; 35 36 def MMX_PHADDSUBD : OpndItins< 37 IIC_MMX_PHADDSUBD_RR, IIC_MMX_PHADDSUBD_RM 38 >; 39 } 40 41 let Sched = WriteVecIMul in 42 def MMX_PMUL_ITINS : OpndItins< 43 IIC_MMX_PMUL, IIC_MMX_PMUL 44 >; 45 46 let Sched = WriteVecALU in { 47 def MMX_PSADBW_ITINS : OpndItins< 48 IIC_MMX_PSADBW, IIC_MMX_PSADBW 49 >; 50 51 def MMX_MISC_FUNC_ITINS : OpndItins< 52 IIC_MMX_MISC_FUNC_MEM, IIC_MMX_MISC_FUNC_REG 53 >; 54 } 55 56 def MMX_SHIFT_ITINS : ShiftOpndItins< 57 IIC_MMX_SHIFT_RR, IIC_MMX_SHIFT_RM, IIC_MMX_SHIFT_RI 58 >; 59 60 let Sched = WriteShuffle in { 61 def MMX_UNPCK_H_ITINS : OpndItins< 62 IIC_MMX_UNPCK_H_RR, IIC_MMX_UNPCK_H_RM 63 >; 64 65 def MMX_UNPCK_L_ITINS : OpndItins< 66 IIC_MMX_UNPCK_L, IIC_MMX_UNPCK_L 67 >; 68 69 def MMX_PCK_ITINS : OpndItins< 70 IIC_MMX_PCK_RR, IIC_MMX_PCK_RM 71 >; 72 73 def MMX_PSHUF_ITINS : OpndItins< 74 IIC_MMX_PSHUF, IIC_MMX_PSHUF 75 >; 76 } // Sched 77 78 let Sched = WriteCvtF2I in { 79 def MMX_CVT_PD_ITINS : OpndItins< 80 IIC_MMX_CVT_PD_RR, IIC_MMX_CVT_PD_RM 81 >; 82 83 def MMX_CVT_PS_ITINS : OpndItins< 84 IIC_MMX_CVT_PS_RR, IIC_MMX_CVT_PS_RM 85 >; 86 } 87 88 let Constraints = "$src1 = $dst" in { 89 // MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic. 90 // When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp. 91 multiclass MMXI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId, 92 OpndItins itins, bit Commutable = 0> { 93 def irr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 94 (ins VR64:$src1, VR64:$src2), 95 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 96 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>, 97 Sched<[itins.Sched]> { 98 let isCommutable = Commutable; 99 } 100 def irm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 101 (ins VR64:$src1, i64mem:$src2), 102 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 103 [(set VR64:$dst, (IntId VR64:$src1, 104 (bitconvert (load_mmx addr:$src2))))], 105 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>; 106 } 107 108 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm, 109 string OpcodeStr, Intrinsic IntId, 110 Intrinsic IntId2, ShiftOpndItins itins> { 111 def rr : MMXI<opc, MRMSrcReg, (outs VR64:$dst), 112 (ins VR64:$src1, VR64:$src2), 113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 114 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>, 115 Sched<[WriteVecShift]>; 116 def rm : MMXI<opc, MRMSrcMem, (outs VR64:$dst), 117 (ins VR64:$src1, i64mem:$src2), 118 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 119 [(set VR64:$dst, (IntId VR64:$src1, 120 (bitconvert (load_mmx addr:$src2))))], 121 itins.rm>, Sched<[WriteVecShiftLd, ReadAfterLd]>; 122 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst), 123 (ins VR64:$src1, i32i8imm:$src2), 124 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 125 [(set VR64:$dst, (IntId2 VR64:$src1, (i32 imm:$src2)))], itins.ri>, 126 Sched<[WriteVecShift]>; 127 } 128 } 129 130 /// Unary MMX instructions requiring SSSE3. 131 multiclass SS3I_unop_rm_int_mm<bits<8> opc, string OpcodeStr, 132 Intrinsic IntId64, OpndItins itins> { 133 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 134 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 135 [(set VR64:$dst, (IntId64 VR64:$src))], itins.rr>, 136 Sched<[itins.Sched]>; 137 138 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 139 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), 140 [(set VR64:$dst, 141 (IntId64 (bitconvert (memopmmx addr:$src))))], 142 itins.rm>, Sched<[itins.Sched.Folded]>; 143 } 144 145 /// Binary MMX instructions requiring SSSE3. 146 let ImmT = NoImm, Constraints = "$src1 = $dst" in { 147 multiclass SS3I_binop_rm_int_mm<bits<8> opc, string OpcodeStr, 148 Intrinsic IntId64, OpndItins itins> { 149 let isCommutable = 0 in 150 def rr64 : MMXSS38I<opc, MRMSrcReg, (outs VR64:$dst), 151 (ins VR64:$src1, VR64:$src2), 152 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 153 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))], itins.rr>, 154 Sched<[itins.Sched]>; 155 def rm64 : MMXSS38I<opc, MRMSrcMem, (outs VR64:$dst), 156 (ins VR64:$src1, i64mem:$src2), 157 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"), 158 [(set VR64:$dst, 159 (IntId64 VR64:$src1, 160 (bitconvert (memopmmx addr:$src2))))], itins.rm>, 161 Sched<[itins.Sched.Folded, ReadAfterLd]>; 162 } 163 } 164 165 /// PALIGN MMX instructions (require SSSE3). 166 multiclass ssse3_palign_mm<string asm, Intrinsic IntId> { 167 def R64irr : MMXSS3AI<0x0F, MRMSrcReg, (outs VR64:$dst), 168 (ins VR64:$src1, VR64:$src2, i8imm:$src3), 169 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 170 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2, (i8 imm:$src3)))]>; 171 def R64irm : MMXSS3AI<0x0F, MRMSrcMem, (outs VR64:$dst), 172 (ins VR64:$src1, i64mem:$src2, i8imm:$src3), 173 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"), 174 [(set VR64:$dst, (IntId VR64:$src1, 175 (bitconvert (load_mmx addr:$src2)), (i8 imm:$src3)))]>; 176 } 177 178 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC, 179 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag, 180 string asm, OpndItins itins, Domain d> { 181 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm, 182 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>, 183 Sched<[itins.Sched]>; 184 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm, 185 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm, d>, 186 Sched<[itins.Sched.Folded]>; 187 } 188 189 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC, 190 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop, 191 PatFrag ld_frag, string asm, Domain d> { 192 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), 193 (ins DstRC:$src1, SrcRC:$src2), asm, 194 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], 195 NoItinerary, d>; 196 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), 197 (ins DstRC:$src1, x86memop:$src2), asm, 198 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], 199 NoItinerary, d>; 200 } 201 202 //===----------------------------------------------------------------------===// 203 // MMX EMMS Instruction 204 //===----------------------------------------------------------------------===// 205 206 def MMX_EMMS : MMXI<0x77, RawFrm, (outs), (ins), "emms", 207 [(int_x86_mmx_emms)], IIC_MMX_EMMS>; 208 209 //===----------------------------------------------------------------------===// 210 // MMX Scalar Instructions 211 //===----------------------------------------------------------------------===// 212 213 // Data Transfer Instructions 214 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src), 215 "movd\t{$src, $dst|$dst, $src}", 216 [(set VR64:$dst, 217 (x86mmx (scalar_to_vector GR32:$src)))], 218 IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>; 219 let canFoldAsLoad = 1 in 220 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src), 221 "movd\t{$src, $dst|$dst, $src}", 222 [(set VR64:$dst, 223 (x86mmx (scalar_to_vector (loadi32 addr:$src))))], 224 IIC_MMX_MOV_MM_RM>, Sched<[WriteLoad]>; 225 let mayStore = 1 in 226 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src), 227 "movd\t{$src, $dst|$dst, $src}", [], IIC_MMX_MOV_MM_RM>, 228 Sched<[WriteStore]>; 229 230 // Low word of MMX to GPR. 231 def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1, 232 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>; 233 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR64:$src), 234 "movd\t{$src, $dst|$dst, $src}", 235 [(set GR32:$dst, 236 (MMX_X86movd2w (x86mmx VR64:$src)))], 237 IIC_MMX_MOV_REG_MM>, Sched<[WriteMove]>; 238 239 def MMX_MOVD64to64rr : MMXRI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR64:$src), 240 "movd\t{$src, $dst|$dst, $src}", 241 [(set VR64:$dst, (bitconvert GR64:$src))], 242 IIC_MMX_MOV_MM_RM>, Sched<[WriteMove]>; 243 244 // These are 64 bit moves, but since the OS X assembler doesn't 245 // recognize a register-register movq, we write them as 246 // movd. 247 let SchedRW = [WriteMove] in { 248 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg, 249 (outs GR64:$dst), (ins VR64:$src), 250 "movd\t{$src, $dst|$dst, $src}", 251 [(set GR64:$dst, 252 (bitconvert VR64:$src))], IIC_MMX_MOV_REG_MM>; 253 let neverHasSideEffects = 1 in 254 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src), 255 "movq\t{$src, $dst|$dst, $src}", [], 256 IIC_MMX_MOVQ_RR>; 257 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 258 def MMX_MOVQ64rr_REV : MMXI<0x7F, MRMDestReg, (outs VR64:$dst), (ins VR64:$src), 259 "movq\t{$src, $dst|$dst, $src}", [], 260 IIC_MMX_MOVQ_RR>; 261 } 262 } // SchedRW 263 264 let SchedRW = [WriteLoad] in { 265 let canFoldAsLoad = 1 in 266 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src), 267 "movq\t{$src, $dst|$dst, $src}", 268 [(set VR64:$dst, (load_mmx addr:$src))], 269 IIC_MMX_MOVQ_RM>; 270 } // SchedRW 271 let SchedRW = [WriteStore] in 272 def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), 273 "movq\t{$src, $dst|$dst, $src}", 274 [(store (x86mmx VR64:$src), addr:$dst)], 275 IIC_MMX_MOVQ_RM>; 276 277 let SchedRW = [WriteMove] in { 278 def MMX_MOVDQ2Qrr : MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), 279 (ins VR128:$src), "movdq2q\t{$src, $dst|$dst, $src}", 280 [(set VR64:$dst, 281 (x86mmx (bitconvert 282 (i64 (vector_extract (v2i64 VR128:$src), 283 (iPTR 0))))))], 284 IIC_MMX_MOVQ_RR>; 285 286 def MMX_MOVQ2DQrr : MMXS2SIi8<0xD6, MRMSrcReg, (outs VR128:$dst), 287 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", 288 [(set VR128:$dst, 289 (v2i64 290 (scalar_to_vector 291 (i64 (bitconvert (x86mmx VR64:$src))))))], 292 IIC_MMX_MOVQ_RR>; 293 294 let isCodeGenOnly = 1, hasSideEffects = 1 in { 295 def MMX_MOVQ2FR64rr: MMXS2SIi8<0xD6, MRMSrcReg, (outs FR64:$dst), 296 (ins VR64:$src), "movq2dq\t{$src, $dst|$dst, $src}", 297 [], IIC_MMX_MOVQ_RR>; 298 299 def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMSrcReg, (outs VR64:$dst), 300 (ins FR64:$src), "movdq2q\t{$src, $dst|$dst, $src}", 301 [], IIC_MMX_MOVQ_RR>; 302 } 303 } // SchedRW 304 305 def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src), 306 "movntq\t{$src, $dst|$dst, $src}", 307 [(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)], 308 IIC_MMX_MOVQ_RM>, Sched<[WriteStore]>; 309 310 let Predicates = [HasMMX] in { 311 let AddedComplexity = 15 in 312 // movd to MMX register zero-extends 313 def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector GR32:$src)))), 314 (MMX_MOVD64rr GR32:$src)>; 315 let AddedComplexity = 20 in 316 def : Pat<(x86mmx (X86vzmovl (x86mmx (scalar_to_vector (loadi32 addr:$src))))), 317 (MMX_MOVD64rm addr:$src)>; 318 } 319 320 // Arithmetic Instructions 321 defm MMX_PABSB : SS3I_unop_rm_int_mm<0x1C, "pabsb", int_x86_ssse3_pabs_b, 322 MMX_INTALU_ITINS>; 323 defm MMX_PABSW : SS3I_unop_rm_int_mm<0x1D, "pabsw", int_x86_ssse3_pabs_w, 324 MMX_INTALU_ITINS>; 325 defm MMX_PABSD : SS3I_unop_rm_int_mm<0x1E, "pabsd", int_x86_ssse3_pabs_d, 326 MMX_INTALU_ITINS>; 327 // -- Addition 328 defm MMX_PADDB : MMXI_binop_rm_int<0xFC, "paddb", int_x86_mmx_padd_b, 329 MMX_INTALU_ITINS, 1>; 330 defm MMX_PADDW : MMXI_binop_rm_int<0xFD, "paddw", int_x86_mmx_padd_w, 331 MMX_INTALU_ITINS, 1>; 332 defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d, 333 MMX_INTALU_ITINS, 1>; 334 defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q, 335 MMX_INTALUQ_ITINS, 1>; 336 defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b, 337 MMX_INTALU_ITINS, 1>; 338 defm MMX_PADDSW : MMXI_binop_rm_int<0xED, "paddsw" , int_x86_mmx_padds_w, 339 MMX_INTALU_ITINS, 1>; 340 341 defm MMX_PADDUSB : MMXI_binop_rm_int<0xDC, "paddusb", int_x86_mmx_paddus_b, 342 MMX_INTALU_ITINS, 1>; 343 defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 344 MMX_INTALU_ITINS, 1>; 345 346 defm MMX_PHADDW : SS3I_binop_rm_int_mm<0x01, "phaddw", int_x86_ssse3_phadd_w, 347 MMX_PHADDSUBW>; 348 defm MMX_PHADD : SS3I_binop_rm_int_mm<0x02, "phaddd", int_x86_ssse3_phadd_d, 349 MMX_PHADDSUBD>; 350 defm MMX_PHADDSW : SS3I_binop_rm_int_mm<0x03, "phaddsw",int_x86_ssse3_phadd_sw, 351 MMX_PHADDSUBW>; 352 353 354 // -- Subtraction 355 defm MMX_PSUBB : MMXI_binop_rm_int<0xF8, "psubb", int_x86_mmx_psub_b, 356 MMX_INTALU_ITINS>; 357 defm MMX_PSUBW : MMXI_binop_rm_int<0xF9, "psubw", int_x86_mmx_psub_w, 358 MMX_INTALU_ITINS>; 359 defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d, 360 MMX_INTALU_ITINS>; 361 defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q, 362 MMX_INTALUQ_ITINS>; 363 364 defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b, 365 MMX_INTALU_ITINS>; 366 defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w, 367 MMX_INTALU_ITINS>; 368 369 defm MMX_PSUBUSB : MMXI_binop_rm_int<0xD8, "psubusb", int_x86_mmx_psubus_b, 370 MMX_INTALU_ITINS>; 371 defm MMX_PSUBUSW : MMXI_binop_rm_int<0xD9, "psubusw", int_x86_mmx_psubus_w, 372 MMX_INTALU_ITINS>; 373 374 defm MMX_PHSUBW : SS3I_binop_rm_int_mm<0x05, "phsubw", int_x86_ssse3_phsub_w, 375 MMX_PHADDSUBW>; 376 defm MMX_PHSUBD : SS3I_binop_rm_int_mm<0x06, "phsubd", int_x86_ssse3_phsub_d, 377 MMX_PHADDSUBD>; 378 defm MMX_PHSUBSW : SS3I_binop_rm_int_mm<0x07, "phsubsw",int_x86_ssse3_phsub_sw, 379 MMX_PHADDSUBW>; 380 381 // -- Multiplication 382 defm MMX_PMULLW : MMXI_binop_rm_int<0xD5, "pmullw", int_x86_mmx_pmull_w, 383 MMX_PMUL_ITINS, 1>; 384 385 defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w, 386 MMX_PMUL_ITINS, 1>; 387 defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w, 388 MMX_PMUL_ITINS, 1>; 389 defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq, 390 MMX_PMUL_ITINS, 1>; 391 let isCommutable = 1 in 392 defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw", 393 int_x86_ssse3_pmul_hr_sw, MMX_PMUL_ITINS>; 394 395 // -- Miscellanea 396 defm MMX_PMADDWD : MMXI_binop_rm_int<0xF5, "pmaddwd", int_x86_mmx_pmadd_wd, 397 MMX_PMUL_ITINS, 1>; 398 399 defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw", 400 int_x86_ssse3_pmadd_ub_sw, MMX_PMUL_ITINS>; 401 defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b, 402 MMX_MISC_FUNC_ITINS, 1>; 403 defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w, 404 MMX_MISC_FUNC_ITINS, 1>; 405 406 defm MMX_PMINUB : MMXI_binop_rm_int<0xDA, "pminub", int_x86_mmx_pminu_b, 407 MMX_MISC_FUNC_ITINS, 1>; 408 defm MMX_PMINSW : MMXI_binop_rm_int<0xEA, "pminsw", int_x86_mmx_pmins_w, 409 MMX_MISC_FUNC_ITINS, 1>; 410 411 defm MMX_PMAXUB : MMXI_binop_rm_int<0xDE, "pmaxub", int_x86_mmx_pmaxu_b, 412 MMX_MISC_FUNC_ITINS, 1>; 413 defm MMX_PMAXSW : MMXI_binop_rm_int<0xEE, "pmaxsw", int_x86_mmx_pmaxs_w, 414 MMX_MISC_FUNC_ITINS, 1>; 415 416 defm MMX_PSADBW : MMXI_binop_rm_int<0xF6, "psadbw", int_x86_mmx_psad_bw, 417 MMX_PSADBW_ITINS, 1>; 418 419 defm MMX_PSIGNB : SS3I_binop_rm_int_mm<0x08, "psignb", int_x86_ssse3_psign_b, 420 MMX_MISC_FUNC_ITINS>; 421 defm MMX_PSIGNW : SS3I_binop_rm_int_mm<0x09, "psignw", int_x86_ssse3_psign_w, 422 MMX_MISC_FUNC_ITINS>; 423 defm MMX_PSIGND : SS3I_binop_rm_int_mm<0x0A, "psignd", int_x86_ssse3_psign_d, 424 MMX_MISC_FUNC_ITINS>; 425 let Constraints = "$src1 = $dst" in 426 defm MMX_PALIGN : ssse3_palign_mm<"palignr", int_x86_mmx_palignr_b>; 427 428 // Logical Instructions 429 defm MMX_PAND : MMXI_binop_rm_int<0xDB, "pand", int_x86_mmx_pand, 430 MMX_INTALU_ITINS, 1>; 431 defm MMX_POR : MMXI_binop_rm_int<0xEB, "por" , int_x86_mmx_por, 432 MMX_INTALU_ITINS, 1>; 433 defm MMX_PXOR : MMXI_binop_rm_int<0xEF, "pxor", int_x86_mmx_pxor, 434 MMX_INTALU_ITINS, 1>; 435 defm MMX_PANDN : MMXI_binop_rm_int<0xDF, "pandn", int_x86_mmx_pandn, 436 MMX_INTALU_ITINS>; 437 438 // Shift Instructions 439 defm MMX_PSRLW : MMXI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", 440 int_x86_mmx_psrl_w, int_x86_mmx_psrli_w, 441 MMX_SHIFT_ITINS>; 442 defm MMX_PSRLD : MMXI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", 443 int_x86_mmx_psrl_d, int_x86_mmx_psrli_d, 444 MMX_SHIFT_ITINS>; 445 defm MMX_PSRLQ : MMXI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", 446 int_x86_mmx_psrl_q, int_x86_mmx_psrli_q, 447 MMX_SHIFT_ITINS>; 448 449 defm MMX_PSLLW : MMXI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", 450 int_x86_mmx_psll_w, int_x86_mmx_pslli_w, 451 MMX_SHIFT_ITINS>; 452 defm MMX_PSLLD : MMXI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", 453 int_x86_mmx_psll_d, int_x86_mmx_pslli_d, 454 MMX_SHIFT_ITINS>; 455 defm MMX_PSLLQ : MMXI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", 456 int_x86_mmx_psll_q, int_x86_mmx_pslli_q, 457 MMX_SHIFT_ITINS>; 458 459 defm MMX_PSRAW : MMXI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", 460 int_x86_mmx_psra_w, int_x86_mmx_psrai_w, 461 MMX_SHIFT_ITINS>; 462 defm MMX_PSRAD : MMXI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", 463 int_x86_mmx_psra_d, int_x86_mmx_psrai_d, 464 MMX_SHIFT_ITINS>; 465 466 // Comparison Instructions 467 defm MMX_PCMPEQB : MMXI_binop_rm_int<0x74, "pcmpeqb", int_x86_mmx_pcmpeq_b, 468 MMX_INTALU_ITINS>; 469 defm MMX_PCMPEQW : MMXI_binop_rm_int<0x75, "pcmpeqw", int_x86_mmx_pcmpeq_w, 470 MMX_INTALU_ITINS>; 471 defm MMX_PCMPEQD : MMXI_binop_rm_int<0x76, "pcmpeqd", int_x86_mmx_pcmpeq_d, 472 MMX_INTALU_ITINS>; 473 474 defm MMX_PCMPGTB : MMXI_binop_rm_int<0x64, "pcmpgtb", int_x86_mmx_pcmpgt_b, 475 MMX_INTALU_ITINS>; 476 defm MMX_PCMPGTW : MMXI_binop_rm_int<0x65, "pcmpgtw", int_x86_mmx_pcmpgt_w, 477 MMX_INTALU_ITINS>; 478 defm MMX_PCMPGTD : MMXI_binop_rm_int<0x66, "pcmpgtd", int_x86_mmx_pcmpgt_d, 479 MMX_INTALU_ITINS>; 480 481 // -- Unpack Instructions 482 defm MMX_PUNPCKHBW : MMXI_binop_rm_int<0x68, "punpckhbw", 483 int_x86_mmx_punpckhbw, 484 MMX_UNPCK_H_ITINS>; 485 defm MMX_PUNPCKHWD : MMXI_binop_rm_int<0x69, "punpckhwd", 486 int_x86_mmx_punpckhwd, 487 MMX_UNPCK_H_ITINS>; 488 defm MMX_PUNPCKHDQ : MMXI_binop_rm_int<0x6A, "punpckhdq", 489 int_x86_mmx_punpckhdq, 490 MMX_UNPCK_H_ITINS>; 491 defm MMX_PUNPCKLBW : MMXI_binop_rm_int<0x60, "punpcklbw", 492 int_x86_mmx_punpcklbw, 493 MMX_UNPCK_L_ITINS>; 494 defm MMX_PUNPCKLWD : MMXI_binop_rm_int<0x61, "punpcklwd", 495 int_x86_mmx_punpcklwd, 496 MMX_UNPCK_L_ITINS>; 497 defm MMX_PUNPCKLDQ : MMXI_binop_rm_int<0x62, "punpckldq", 498 int_x86_mmx_punpckldq, 499 MMX_UNPCK_L_ITINS>; 500 501 // -- Pack Instructions 502 defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb, 503 MMX_PCK_ITINS>; 504 defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw, 505 MMX_PCK_ITINS>; 506 defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb, 507 MMX_PCK_ITINS>; 508 509 // -- Shuffle Instructions 510 defm MMX_PSHUFB : SS3I_binop_rm_int_mm<0x00, "pshufb", int_x86_ssse3_pshuf_b, 511 MMX_PSHUF_ITINS>; 512 513 def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg, 514 (outs VR64:$dst), (ins VR64:$src1, i8imm:$src2), 515 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 516 [(set VR64:$dst, 517 (int_x86_sse_pshuf_w VR64:$src1, imm:$src2))], 518 IIC_MMX_PSHUF>, Sched<[WriteShuffle]>; 519 def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem, 520 (outs VR64:$dst), (ins i64mem:$src1, i8imm:$src2), 521 "pshufw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 522 [(set VR64:$dst, 523 (int_x86_sse_pshuf_w (load_mmx addr:$src1), 524 imm:$src2))], 525 IIC_MMX_PSHUF>, Sched<[WriteShuffleLd]>; 526 527 528 529 530 // -- Conversion Instructions 531 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi, 532 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}", 533 MMX_CVT_PS_ITINS, SSEPackedSingle>, PS; 534 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi, 535 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}", 536 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; 537 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi, 538 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}", 539 MMX_CVT_PS_ITINS, SSEPackedSingle>, PS; 540 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi, 541 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}", 542 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; 543 defm MMX_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd, 544 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}", 545 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD; 546 let Constraints = "$src1 = $dst" in { 547 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128, 548 int_x86_sse_cvtpi2ps, 549 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}", 550 SSEPackedSingle>, PS; 551 } 552 553 // Extract / Insert 554 def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg, 555 (outs GR32orGR64:$dst), (ins VR64:$src1, i32i8imm:$src2), 556 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}", 557 [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1, 558 (iPTR imm:$src2)))], 559 IIC_MMX_PEXTR>, Sched<[WriteShuffle]>; 560 let Constraints = "$src1 = $dst" in { 561 def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg, 562 (outs VR64:$dst), 563 (ins VR64:$src1, GR32orGR64:$src2, i32i8imm:$src3), 564 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", 565 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, 566 GR32orGR64:$src2, (iPTR imm:$src3)))], 567 IIC_MMX_PINSRW>, Sched<[WriteShuffle]>; 568 569 def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem, 570 (outs VR64:$dst), 571 (ins VR64:$src1, i16mem:$src2, i32i8imm:$src3), 572 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}", 573 [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1, 574 (i32 (anyext (loadi16 addr:$src2))), 575 (iPTR imm:$src3)))], 576 IIC_MMX_PINSRW>, Sched<[WriteShuffleLd, ReadAfterLd]>; 577 } 578 579 // Mask creation 580 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), 581 (ins VR64:$src), 582 "pmovmskb\t{$src, $dst|$dst, $src}", 583 [(set GR32orGR64:$dst, 584 (int_x86_mmx_pmovmskb VR64:$src))]>; 585 586 587 // Low word of XMM to MMX. 588 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1, 589 [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>; 590 591 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)), 592 (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>; 593 594 def : Pat<(x86mmx (MMX_X86movdq2q (loadv2i64 addr:$src))), 595 (x86mmx (MMX_MOVQ64rm addr:$src))>; 596 597 // Misc. 598 let SchedRW = [WriteShuffle] in { 599 let Uses = [EDI] in 600 def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), 601 "maskmovq\t{$mask, $src|$src, $mask}", 602 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)], 603 IIC_MMX_MASKMOV>; 604 let Uses = [RDI] in 605 def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask), 606 "maskmovq\t{$mask, $src|$src, $mask}", 607 [(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)], 608 IIC_MMX_MASKMOV>; 609 } 610 611 // 64-bit bit convert. 612 let Predicates = [HasSSE2] in { 613 def : Pat<(x86mmx (bitconvert (i64 GR64:$src))), 614 (MMX_MOVD64to64rr GR64:$src)>; 615 def : Pat<(i64 (bitconvert (x86mmx VR64:$src))), 616 (MMX_MOVD64from64rr VR64:$src)>; 617 def : Pat<(f64 (bitconvert (x86mmx VR64:$src))), 618 (MMX_MOVQ2FR64rr VR64:$src)>; 619 def : Pat<(x86mmx (bitconvert (f64 FR64:$src))), 620 (MMX_MOVFR642Qrr FR64:$src)>; 621 } 622 623 624
