1 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM 2 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM 3 ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB 4 5 define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind { 6 entry: 7 ; ARM: icmp_i16_signed 8 ; ARM: sxth r0, r0 9 ; ARM: sxth r1, r1 10 ; ARM: cmp r0, r1 11 ; THUMB: icmp_i16_signed 12 ; THUMB: sxth r0, r0 13 ; THUMB: sxth r1, r1 14 ; THUMB: cmp r0, r1 15 %cmp = icmp slt i16 %a, %b 16 %conv2 = zext i1 %cmp to i32 17 ret i32 %conv2 18 } 19 20 define i32 @icmp_i16_unsigned(i16 %a, i16 %b) nounwind { 21 entry: 22 ; ARM: icmp_i16_unsigned 23 ; ARM: uxth r0, r0 24 ; ARM: uxth r1, r1 25 ; ARM: cmp r0, r1 26 ; THUMB: icmp_i16_unsigned 27 ; THUMB: uxth r0, r0 28 ; THUMB: uxth r1, r1 29 ; THUMB: cmp r0, r1 30 %cmp = icmp ult i16 %a, %b 31 %conv2 = zext i1 %cmp to i32 32 ret i32 %conv2 33 } 34 35 define i32 @icmp_i8_signed(i8 %a, i8 %b) nounwind { 36 entry: 37 ; ARM: icmp_i8_signed 38 ; ARM: sxtb r0, r0 39 ; ARM: sxtb r1, r1 40 ; ARM: cmp r0, r1 41 ; THUMB: icmp_i8_signed 42 ; THUMB: sxtb r0, r0 43 ; THUMB: sxtb r1, r1 44 ; THUMB: cmp r0, r1 45 %cmp = icmp sgt i8 %a, %b 46 %conv2 = zext i1 %cmp to i32 47 ret i32 %conv2 48 } 49 50 define i32 @icmp_i8_unsigned(i8 %a, i8 %b) nounwind { 51 entry: 52 ; ARM: icmp_i8_unsigned 53 ; ARM: and r0, r0, #255 54 ; ARM: and r1, r1, #255 55 ; ARM: cmp r0, r1 56 ; THUMB: icmp_i8_unsigned 57 ; THUMB: and r0, r0, #255 58 ; THUMB: and r1, r1, #255 59 ; THUMB: cmp r0, r1 60 %cmp = icmp ugt i8 %a, %b 61 %conv2 = zext i1 %cmp to i32 62 ret i32 %conv2 63 } 64 65 define i32 @icmp_i1_unsigned(i1 %a, i1 %b) nounwind { 66 entry: 67 ; ARM: icmp_i1_unsigned 68 ; ARM: and r0, r0, #1 69 ; ARM: and r1, r1, #1 70 ; ARM: cmp r0, r1 71 ; THUMB: icmp_i1_unsigned 72 ; THUMB: and r0, r0, #1 73 ; THUMB: and r1, r1, #1 74 ; THUMB: cmp r0, r1 75 %cmp = icmp ult i1 %a, %b 76 %conv2 = zext i1 %cmp to i32 77 ret i32 %conv2 78 } 79
