1 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=A8 -check-prefix=CHECK 2 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK 3 ; rdar://6949835 4 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK 5 ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK 6 7 ; Magic ARM pair hints works best with linearscan / fast. 8 9 ; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base 10 ; register when interrupted or faulted. 11 12 @b = external global i64* 13 14 define i64 @t(i64 %a) nounwind readonly { 15 entry: 16 ; A8-LABEL: t: 17 ; A8: ldrd r2, r3, [r2] 18 19 ; M3-LABEL: t: 20 ; M3-NOT: ldrd 21 22 %0 = load i64** @b, align 4 23 %1 = load i64* %0, align 4 24 %2 = mul i64 %1, %a 25 ret i64 %2 26 } 27 28 ; rdar://10435045 mixed LDRi8/LDRi12 29 ; 30 ; In this case, LSR generate a sequence of LDRi8/LDRi12. We should be 31 ; able to generate an LDRD pair here, but this is highly sensitive to 32 ; regalloc hinting. So, this doubles as a register allocation 33 ; test. RABasic currently does a better job within the inner loop 34 ; because of its *lack* of hinting ability. Whereas RAGreedy keeps 35 ; R0/R1/R2 live as the three arguments, forcing the LDRD's odd 36 ; destination into R3. We then sensibly split LDRD again rather then 37 ; evict another live range or use callee saved regs. Sorry if the test 38 ; is sensitive to Regalloc changes, but it is an interesting case. 39 ; 40 ; BASIC: @f 41 ; BASIC: %bb 42 ; BASIC: ldrd 43 ; BASIC: str 44 ; GREEDY: @f 45 ; GREEDY: %bb 46 ; GREEDY: ldrd 47 ; GREEDY: str 48 define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind { 49 entry: 50 %0 = add nsw i32 %n, -1 ; <i32> [#uses=2] 51 %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1] 52 br i1 %1, label %bb, label %return 53 54 bb: ; preds = %bb, %entry 55 %i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3] 56 %scevgep = getelementptr i32* %a, i32 %i.03 ; <i32*> [#uses=1] 57 %scevgep4 = getelementptr i32* %b, i32 %i.03 ; <i32*> [#uses=1] 58 %tmp = add i32 %i.03, 1 ; <i32> [#uses=3] 59 %scevgep5 = getelementptr i32* %a, i32 %tmp ; <i32*> [#uses=1] 60 %2 = load i32* %scevgep, align 4 ; <i32> [#uses=1] 61 %3 = load i32* %scevgep5, align 4 ; <i32> [#uses=1] 62 %4 = add nsw i32 %3, %2 ; <i32> [#uses=1] 63 store i32 %4, i32* %scevgep4, align 4 64 %exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1] 65 br i1 %exitcond, label %return, label %bb 66 67 return: ; preds = %bb, %entry 68 ret void 69 } 70 71 ; rdar://13978317 72 ; Pair of loads not formed when lifetime markers are set. 73 %struct.Test = type { i32, i32, i32 } 74 75 @TestVar = external global %struct.Test 76 77 define void @Func1() nounwind ssp { 78 ; CHECK: @Func1 79 entry: 80 ; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}} 81 ; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}} 82 ; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4] 83 ; A8-NEXT: add [[FIELD1]], [[FIELD2]] 84 ; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}} 85 %orig_blocks = alloca [256 x i16], align 2 86 %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind 87 %tmp1 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 1), align 4 88 %tmp2 = load i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 2), align 4 89 %add = add nsw i32 %tmp2, %tmp1 90 store i32 %add, i32* getelementptr inbounds (%struct.Test* @TestVar, i32 0, i32 0), align 4 91 call void @llvm.lifetime.end(i64 512, i8* %0) nounwind 92 ret void 93 } 94 95 96 declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind 97 declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind 98
