1 ; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 -check-prefix=ACCMULDIV %s 2 ; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s 3 ; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s 4 ; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=GPRMULDIV %s 5 6 @gll0 = common global i64 0, align 8 7 @gll1 = common global i64 0, align 8 8 9 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone { 10 entry: 11 ; ALL-LABEL: f0: 12 ; ALL: daddu $2, ${{[45]}}, ${{[45]}} 13 %add = add nsw i64 %a1, %a0 14 ret i64 %add 15 } 16 17 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone { 18 entry: 19 ; ALL-LABEL: f1: 20 ; ALL: dsubu $2, $4, $5 21 %sub = sub nsw i64 %a0, %a1 22 ret i64 %sub 23 } 24 25 define i64 @f4(i64 %a0, i64 %a1) nounwind readnone { 26 entry: 27 ; ALL-LABEL: f4: 28 ; ALL: and $2, ${{[45]}}, ${{[45]}} 29 %and = and i64 %a1, %a0 30 ret i64 %and 31 } 32 33 define i64 @f5(i64 %a0, i64 %a1) nounwind readnone { 34 entry: 35 ; ALL-LABEL: f5: 36 ; ALL: or $2, ${{[45]}}, ${{[45]}} 37 %or = or i64 %a1, %a0 38 ret i64 %or 39 } 40 41 define i64 @f6(i64 %a0, i64 %a1) nounwind readnone { 42 entry: 43 ; ALL-LABEL: f6: 44 ; ALL: xor $2, ${{[45]}}, ${{[45]}} 45 %xor = xor i64 %a1, %a0 46 ret i64 %xor 47 } 48 49 define i64 @f7(i64 %a0) nounwind readnone { 50 entry: 51 ; ALL-LABEL: f7: 52 ; ALL: daddiu $2, $4, 20 53 %add = add nsw i64 %a0, 20 54 ret i64 %add 55 } 56 57 define i64 @f8(i64 %a0) nounwind readnone { 58 entry: 59 ; ALL-LABEL: f8: 60 ; ALL: daddiu $2, $4, -20 61 %sub = add nsw i64 %a0, -20 62 ret i64 %sub 63 } 64 65 define i64 @f9(i64 %a0) nounwind readnone { 66 entry: 67 ; ALL-LABEL: f9: 68 ; ALL: andi $2, $4, 20 69 %and = and i64 %a0, 20 70 ret i64 %and 71 } 72 73 define i64 @f10(i64 %a0) nounwind readnone { 74 entry: 75 ; ALL-LABEL: f10: 76 ; ALL: ori $2, $4, 20 77 %or = or i64 %a0, 20 78 ret i64 %or 79 } 80 81 define i64 @f11(i64 %a0) nounwind readnone { 82 entry: 83 ; ALL-LABEL: f11: 84 ; ALL: xori $2, $4, 20 85 %xor = xor i64 %a0, 20 86 ret i64 %xor 87 } 88 89 define i64 @f12(i64 %a, i64 %b) nounwind readnone { 90 entry: 91 ; ALL-LABEL: f12: 92 93 ; ACCMULDIV: mult ${{[45]}}, ${{[45]}} 94 ; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}} 95 96 %mul = mul nsw i64 %b, %a 97 ret i64 %mul 98 } 99 100 define i64 @f13(i64 %a, i64 %b) nounwind readnone { 101 entry: 102 ; ALL-LABEL: f13: 103 104 ; ACCMULDIV: mult ${{[45]}}, ${{[45]}} 105 ; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}} 106 107 %mul = mul i64 %b, %a 108 ret i64 %mul 109 } 110 111 define i64 @f14(i64 %a, i64 %b) nounwind readnone { 112 entry: 113 ; ALL-LABEL: f14: 114 ; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)( 115 ; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)( 116 ; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]]) 117 ; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]]) 118 119 ; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]] 120 ; ACCMULDIV: teq $[[T1]], $zero, 7 121 ; ACCMULDIV: mflo $2 122 123 ; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]] 124 ; GPRMULDIV: teq $[[T1]], $zero, 7 125 126 %0 = load i64* @gll0, align 8 127 %1 = load i64* @gll1, align 8 128 %div = sdiv i64 %0, %1 129 ret i64 %div 130 } 131 132 define i64 @f15() nounwind readnone { 133 entry: 134 ; ALL-LABEL: f15: 135 ; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)( 136 ; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)( 137 ; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]]) 138 ; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]]) 139 140 ; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]] 141 ; ACCMULDIV: teq $[[T1]], $zero, 7 142 ; ACCMULDIV: mflo $2 143 144 ; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]] 145 ; GPRMULDIV: teq $[[T1]], $zero, 7 146 147 %0 = load i64* @gll0, align 8 148 %1 = load i64* @gll1, align 8 149 %div = udiv i64 %0, %1 150 ret i64 %div 151 } 152 153 define i64 @f16(i64 %a, i64 %b) nounwind readnone { 154 entry: 155 ; ALL-LABEL: f16: 156 157 ; ACCMULDIV: ddiv $zero, $4, $5 158 ; ACCMULDIV: teq $5, $zero, 7 159 ; ACCMULDIV: mfhi $2 160 161 ; GPRMULDIV: dmod $2, $4, $5 162 ; GPRMULDIV: teq $5, $zero, 7 163 164 %rem = srem i64 %a, %b 165 ret i64 %rem 166 } 167 168 define i64 @f17(i64 %a, i64 %b) nounwind readnone { 169 entry: 170 ; ALL-LABEL: f17: 171 172 ; ACCMULDIV: ddivu $zero, $4, $5 173 ; ACCMULDIV: teq $5, $zero, 7 174 ; ACCMULDIV: mfhi $2 175 176 ; GPRMULDIV: dmodu $2, $4, $5 177 ; GPRMULDIV: teq $5, $zero, 7 178 179 %rem = urem i64 %a, %b 180 ret i64 %rem 181 } 182 183 declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 184 185 define i64 @f18(i64 %X) nounwind readnone { 186 entry: 187 ; ALL-LABEL: f18: 188 189 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclz 190 ; MIPS4-NOT: dclz 191 192 ; HAS-DCLO: dclz $2, $4 193 194 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true) 195 ret i64 %tmp1 196 } 197 198 define i64 @f19(i64 %X) nounwind readnone { 199 entry: 200 ; ALL-LABEL: f19: 201 202 ; The MIPS4 version is too long to reasonably test. At least check we don't get dclo 203 ; MIPS4-NOT: dclo 204 205 ; HAS-DCLO: dclo $2, $4 206 207 %neg = xor i64 %X, -1 208 %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true) 209 ret i64 %tmp1 210 } 211 212 define i64 @f20(i64 %a, i64 %b) nounwind readnone { 213 entry: 214 ; ALL-LABEL: f20: 215 ; ALL: nor $2, ${{[45]}}, ${{[45]}} 216 %or = or i64 %b, %a 217 %neg = xor i64 %or, -1 218 ret i64 %neg 219 } 220
