1 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s 2 target datalayout = "E-m:e-i64:64-n32:64" 3 target triple = "powerpc64-unknown-linux-gnu" 4 5 ; Function Attrs: nounwind readnone 6 define zeroext i1 @test1(float %v1, float %v2) #0 { 7 entry: 8 %cmp = fcmp oge float %v1, %v2 9 %cmp2 = fcmp ole float %v2, 0.000000e+00 10 %and5 = and i1 %cmp, %cmp2 11 ret i1 %and5 12 13 ; CHECK-LABEL: @test1 14 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 15 ; CHECK-DAG: li [[REG1:[0-9]+]], 1 16 ; CHECK-DAG: lfs [[REG2:[0-9]+]], 17 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 18 ; CHECK: crnor 19 ; CHECK: crnor 20 ; CHECK: crnand [[REG4:[0-9]+]], 21 ; CHECK: isel 3, 0, [[REG1]], [[REG4]] 22 ; CHECK: blr 23 } 24 25 ; Function Attrs: nounwind readnone 26 define zeroext i1 @test2(float %v1, float %v2) #0 { 27 entry: 28 %cmp = fcmp oge float %v1, %v2 29 %cmp2 = fcmp ole float %v2, 0.000000e+00 30 %xor5 = xor i1 %cmp, %cmp2 31 ret i1 %xor5 32 33 ; CHECK-LABEL: @test2 34 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 35 ; CHECK-DAG: li [[REG1:[0-9]+]], 1 36 ; CHECK-DAG: lfs [[REG2:[0-9]+]], 37 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 38 ; CHECK: crnor 39 ; CHECK: crnor 40 ; CHECK: creqv [[REG4:[0-9]+]], 41 ; CHECK: isel 3, 0, [[REG1]], [[REG4]] 42 ; CHECK: blr 43 } 44 45 ; Function Attrs: nounwind readnone 46 define zeroext i1 @test3(float %v1, float %v2, i32 signext %x) #0 { 47 entry: 48 %cmp = fcmp oge float %v1, %v2 49 %cmp2 = fcmp ole float %v2, 0.000000e+00 50 %cmp4 = icmp ne i32 %x, -2 51 %and7 = and i1 %cmp2, %cmp4 52 %xor8 = xor i1 %cmp, %and7 53 ret i1 %xor8 54 55 ; CHECK-LABEL: @test3 56 ; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2 57 ; CHECK-DAG: li [[REG1:[0-9]+]], 1 58 ; CHECK-DAG: lfs [[REG2:[0-9]+]], 59 ; CHECK-DAG: fcmpu {{[0-9]+}}, 2, [[REG2]] 60 ; CHECK: crnor 61 ; CHECK: crnor 62 ; CHECK: crandc 63 ; CHECK: creqv [[REG4:[0-9]+]], 64 ; CHECK: isel 3, 0, [[REG1]], [[REG4]] 65 ; CHECK: blr 66 } 67 68 ; Function Attrs: nounwind readnone 69 define zeroext i1 @test4(i1 zeroext %v1, i1 zeroext %v2, i1 zeroext %v3) #0 { 70 entry: 71 %and8 = and i1 %v1, %v2 72 %or9 = or i1 %and8, %v3 73 ret i1 %or9 74 75 ; CHECK-DAG: @test4 76 ; CHECK: and [[REG1:[0-9]+]], 3, 4 77 ; CHECK: or 3, [[REG1]], 5 78 ; CHECK: blr 79 } 80 81 ; Function Attrs: nounwind readnone 82 define zeroext i1 @test5(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 { 83 entry: 84 %and6 = and i1 %v1, %v2 85 %cmp = icmp ne i32 %v3, -2 86 %or7 = or i1 %and6, %cmp 87 ret i1 %or7 88 89 ; CHECK-LABEL: @test5 90 ; CHECK-DAG: and [[REG1:[0-9]+]], 3, 4 91 ; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2 92 ; CHECK-DAG: li [[REG3:[0-9]+]], 1 93 ; CHECK-DAG: andi. {{[0-9]+}}, [[REG1]], 1 94 ; CHECK-DAG: crandc [[REG5:[0-9]+]], 95 ; CHECK: isel 3, 0, [[REG3]], [[REG5]] 96 ; CHECK: blr 97 } 98 99 ; Function Attrs: nounwind readnone 100 define zeroext i1 @test6(i1 zeroext %v1, i1 zeroext %v2, i32 signext %v3) #0 { 101 entry: 102 %cmp = icmp ne i32 %v3, -2 103 %or6 = or i1 %cmp, %v2 104 %and7 = and i1 %or6, %v1 105 ret i1 %and7 106 107 ; CHECK-LABEL: @test6 108 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 109 ; CHECK-DAG: cmpwi {{[0-9]+}}, 5, -2 110 ; CHECK-DAG: cror [[REG1:[0-9]+]], 1, 1 111 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 112 ; CHECK-DAG: li [[REG2:[0-9]+]], 1 113 ; CHECK-DAG: crorc [[REG4:[0-9]+]], 1, 114 ; CHECK-DAG: crnand [[REG5:[0-9]+]], [[REG4]], [[REG1]] 115 ; CHECK: isel 3, 0, [[REG2]], [[REG5]] 116 ; CHECK: blr 117 } 118 119 ; Function Attrs: nounwind readnone 120 define signext i32 @test7(i1 zeroext %v2, i32 signext %i1, i32 signext %i2) #0 { 121 entry: 122 %cond = select i1 %v2, i32 %i1, i32 %i2 123 ret i32 %cond 124 125 ; CHECK-LABEL: @test7 126 ; CHECK: andi. {{[0-9]+}}, 3, 1 127 ; CHECK: isel 3, 4, 5, 1 128 ; CHECK: blr 129 } 130 131 define signext i32 @exttest7(i32 signext %a) #0 { 132 entry: 133 %cmp = icmp eq i32 %a, 5 134 %cond = select i1 %cmp, i32 7, i32 8 135 ret i32 %cond 136 137 ; CHECK-LABEL: @exttest7 138 ; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 5 139 ; CHECK-DAG: li [[REG1:[0-9]+]], 8 140 ; CHECK-DAG: li [[REG2:[0-9]+]], 7 141 ; CHECK: isel 3, [[REG2]], [[REG1]], 142 ; CHECK-NOT: rldicl 143 ; CHECK: blr 144 } 145 146 define zeroext i32 @exttest8() #0 { 147 entry: 148 %v0 = load i64* undef, align 8 149 %sub = sub i64 80, %v0 150 %div = lshr i64 %sub, 1 151 %conv13 = trunc i64 %div to i32 152 %cmp14 = icmp ugt i32 %conv13, 80 153 %.conv13 = select i1 %cmp14, i32 0, i32 %conv13 154 ret i32 %.conv13 155 ; CHECK-LABEL: @exttest8 156 ; This is a don't-crash test: %conv13 is both one of the possible select output 157 ; values and also an input to the conditional feeding it. 158 } 159 160 ; Function Attrs: nounwind readnone 161 define float @test8(i1 zeroext %v2, float %v1, float %v3) #0 { 162 entry: 163 %cond = select i1 %v2, float %v1, float %v3 164 ret float %cond 165 166 ; CHECK-LABEL: @test8 167 ; CHECK: andi. {{[0-9]+}}, 3, 1 168 ; CHECK: bclr 12, 1, 0 169 ; CHECK: fmr 1, 2 170 ; CHECK: blr 171 } 172 173 ; Function Attrs: nounwind readnone 174 define signext i32 @test10(i32 signext %v1, i32 signext %v2) #0 { 175 entry: 176 %tobool = icmp ne i32 %v1, 0 177 %lnot = icmp eq i32 %v2, 0 178 %and3 = and i1 %tobool, %lnot 179 %and = zext i1 %and3 to i32 180 ret i32 %and 181 182 ; CHECK-LABEL: @test10 183 ; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 0 184 ; CHECK-DAG: cmpwi {{[0-9]+}}, 4, 0 185 ; CHECK-DAG: li [[REG2:[0-9]+]], 1 186 ; CHECK-DAG: crorc [[REG3:[0-9]+]], 187 ; CHECK: isel 3, 0, [[REG2]], [[REG3]] 188 ; CHECK: blr 189 } 190 191 attributes #0 = { nounwind readnone } 192 193
