1 ; RUN: llc < %s -mcpu=generic -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s 2 ; RUN: llc < %s -mcpu=generic -force-align-stack -stack-alignment=32 -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s -check-prefix=FORCE-ALIGN 3 ; rdar://11496434 4 5 ; no VLAs or dynamic alignment 6 define i32 @t1() nounwind uwtable ssp { 7 entry: 8 %a = alloca i32, align 4 9 call void @t1_helper(i32* %a) nounwind 10 %0 = load i32* %a, align 4 11 %add = add nsw i32 %0, 13 12 ret i32 %add 13 14 ; CHECK: _t1 15 ; CHECK-NOT: andq $-{{[0-9]+}}, %rsp 16 ; CHECK: leaq [[OFFSET:[0-9]*]](%rsp), %rdi 17 ; CHECK: callq _t1_helper 18 ; CHECK: movl [[OFFSET]](%rsp), %eax 19 ; CHECK: addl $13, %eax 20 } 21 22 declare void @t1_helper(i32*) 23 24 ; dynamic realignment 25 define i32 @t2() nounwind uwtable ssp { 26 entry: 27 %a = alloca i32, align 4 28 %v = alloca <8 x float>, align 32 29 call void @t2_helper(i32* %a, <8 x float>* %v) nounwind 30 %0 = load i32* %a, align 4 31 %add = add nsw i32 %0, 13 32 ret i32 %add 33 34 ; CHECK: _t2 35 ; CHECK: pushq %rbp 36 ; CHECK: movq %rsp, %rbp 37 ; CHECK: andq $-32, %rsp 38 ; CHECK: subq ${{[0-9]+}}, %rsp 39 ; 40 ; CHECK: leaq {{[0-9]*}}(%rsp), %rdi 41 ; CHECK: leaq {{[0-9]*}}(%rsp), %rsi 42 ; CHECK: callq _t2_helper 43 ; 44 ; CHECK: movq %rbp, %rsp 45 ; CHECK: popq %rbp 46 } 47 48 declare void @t2_helper(i32*, <8 x float>*) 49 50 ; VLAs 51 define i32 @t3(i64 %sz) nounwind uwtable ssp { 52 entry: 53 %a = alloca i32, align 4 54 %vla = alloca i32, i64 %sz, align 16 55 call void @t3_helper(i32* %a, i32* %vla) nounwind 56 %0 = load i32* %a, align 4 57 %add = add nsw i32 %0, 13 58 ret i32 %add 59 60 ; CHECK: _t3 61 ; CHECK: pushq %rbp 62 ; CHECK: movq %rsp, %rbp 63 ; CHECK: pushq %rbx 64 ; CHECK-NOT: andq $-{{[0-9]+}}, %rsp 65 ; CHECK: subq ${{[0-9]+}}, %rsp 66 ; 67 ; CHECK: leaq -{{[0-9]+}}(%rbp), %rsp 68 ; CHECK: popq %rbx 69 ; CHECK: popq %rbp 70 } 71 72 declare void @t3_helper(i32*, i32*) 73 74 ; VLAs + Dynamic realignment 75 define i32 @t4(i64 %sz) nounwind uwtable ssp { 76 entry: 77 %a = alloca i32, align 4 78 %v = alloca <8 x float>, align 32 79 %vla = alloca i32, i64 %sz, align 16 80 call void @t4_helper(i32* %a, i32* %vla, <8 x float>* %v) nounwind 81 %0 = load i32* %a, align 4 82 %add = add nsw i32 %0, 13 83 ret i32 %add 84 85 ; CHECK: _t4 86 ; CHECK: pushq %rbp 87 ; CHECK: movq %rsp, %rbp 88 ; CHECK: pushq %r14 89 ; CHECK: pushq %rbx 90 ; CHECK: andq $-32, %rsp 91 ; CHECK: subq ${{[0-9]+}}, %rsp 92 ; CHECK: movq %rsp, %rbx 93 ; 94 ; CHECK: leaq {{[0-9]*}}(%rbx), %rdi 95 ; CHECK: leaq {{[0-9]*}}(%rbx), %rdx 96 ; CHECK: callq _t4_helper 97 ; 98 ; CHECK: leaq -16(%rbp), %rsp 99 ; CHECK: popq %rbx 100 ; CHECK: popq %r14 101 ; CHECK: popq %rbp 102 } 103 104 declare void @t4_helper(i32*, i32*, <8 x float>*) 105 106 ; Spilling an AVX register shouldn't cause dynamic realignment 107 define i32 @t5(float* nocapture %f) nounwind uwtable ssp { 108 entry: 109 %a = alloca i32, align 4 110 %0 = bitcast float* %f to <8 x float>* 111 %1 = load <8 x float>* %0, align 32 112 call void @t5_helper1(i32* %a) nounwind 113 call void @t5_helper2(<8 x float> %1) nounwind 114 %2 = load i32* %a, align 4 115 %add = add nsw i32 %2, 13 116 ret i32 %add 117 118 ; CHECK: _t5 119 ; CHECK: subq ${{[0-9]+}}, %rsp 120 ; 121 ; CHECK: vmovaps (%rdi), [[AVXREG:%ymm[0-9]+]] 122 ; CHECK: vmovups [[AVXREG]], (%rsp) 123 ; CHECK: leaq {{[0-9]+}}(%rsp), %rdi 124 ; CHECK: callq _t5_helper1 125 ; CHECK: vmovups (%rsp), %ymm0 126 ; CHECK: callq _t5_helper2 127 ; CHECK: movl {{[0-9]+}}(%rsp), %eax 128 } 129 130 declare void @t5_helper1(i32*) 131 132 declare void @t5_helper2(<8 x float>) 133 134 ; VLAs + Dynamic realignment + Spill 135 ; FIXME: RA has already reserved RBX, so we can't do dynamic realignment. 136 define i32 @t6(i64 %sz, float* nocapture %f) nounwind uwtable ssp { 137 entry: 138 ; CHECK: _t6 139 %a = alloca i32, align 4 140 %0 = bitcast float* %f to <8 x float>* 141 %1 = load <8 x float>* %0, align 32 142 %vla = alloca i32, i64 %sz, align 16 143 call void @t6_helper1(i32* %a, i32* %vla) nounwind 144 call void @t6_helper2(<8 x float> %1) nounwind 145 %2 = load i32* %a, align 4 146 %add = add nsw i32 %2, 13 147 ret i32 %add 148 } 149 150 declare void @t6_helper1(i32*, i32*) 151 152 declare void @t6_helper2(<8 x float>) 153 154 ; VLAs + Dynamic realignment + byval 155 ; The byval adjust the sp after the prolog, but if we're restoring the sp from 156 ; the base pointer we use the original adjustment. 157 %struct.struct_t = type { [5 x i32] } 158 159 define void @t7(i32 %size, %struct.struct_t* byval align 8 %arg1) nounwind uwtable { 160 entry: 161 %x = alloca i32, align 32 162 store i32 0, i32* %x, align 32 163 %0 = zext i32 %size to i64 164 %vla = alloca i32, i64 %0, align 16 165 %1 = load i32* %x, align 32 166 call void @bar(i32 %1, i32* %vla, %struct.struct_t* byval align 8 %arg1) 167 ret void 168 169 ; CHECK: _t7 170 ; CHECK: pushq %rbp 171 ; CHECK: movq %rsp, %rbp 172 ; CHECK: pushq %rbx 173 ; CHECK: andq $-32, %rsp 174 ; CHECK: subq ${{[0-9]+}}, %rsp 175 ; CHECK: movq %rsp, %rbx 176 177 ; Stack adjustment for byval 178 ; CHECK: subq {{.*}}, %rsp 179 ; CHECK: callq _bar 180 ; CHECK-NOT: addq {{.*}}, %rsp 181 ; CHECK: leaq -8(%rbp), %rsp 182 ; CHECK: popq %rbx 183 ; CHECK: popq %rbp 184 } 185 186 declare i8* @llvm.stacksave() nounwind 187 188 declare void @bar(i32, i32*, %struct.struct_t* byval align 8) 189 190 declare void @llvm.stackrestore(i8*) nounwind 191 192 193 ; Test when forcing stack alignment 194 define i32 @t8() nounwind uwtable { 195 entry: 196 %a = alloca i32, align 4 197 call void @t1_helper(i32* %a) nounwind 198 %0 = load i32* %a, align 4 199 %add = add nsw i32 %0, 13 200 ret i32 %add 201 202 ; FORCE-ALIGN: _t8 203 ; FORCE-ALIGN: movq %rsp, %rbp 204 ; FORCE-ALIGN: andq $-32, %rsp 205 ; FORCE-ALIGN-NEXT: subq $32, %rsp 206 ; FORCE-ALIGN: movq %rbp, %rsp 207 ; FORCE-ALIGN: popq %rbp 208 } 209 210 ; VLAs 211 define i32 @t9(i64 %sz) nounwind uwtable { 212 entry: 213 %a = alloca i32, align 4 214 %vla = alloca i32, i64 %sz, align 16 215 call void @t3_helper(i32* %a, i32* %vla) nounwind 216 %0 = load i32* %a, align 4 217 %add = add nsw i32 %0, 13 218 ret i32 %add 219 220 ; FORCE-ALIGN: _t9 221 ; FORCE-ALIGN: pushq %rbp 222 ; FORCE-ALIGN: movq %rsp, %rbp 223 ; FORCE-ALIGN: pushq %rbx 224 ; FORCE-ALIGN: andq $-32, %rsp 225 ; FORCE-ALIGN: subq $32, %rsp 226 ; FORCE-ALIGN: movq %rsp, %rbx 227 228 ; FORCE-ALIGN: leaq -8(%rbp), %rsp 229 ; FORCE-ALIGN: popq %rbx 230 ; FORCE-ALIGN: popq %rbp 231 } 232
