1 ; RUN: llc < %s -march=xcore | FileCheck %s 2 ; RUN: llc < %s -march=xcore -regalloc=basic | FileCheck %s 3 define i64 @umul_lohi(i32 %a, i32 %b) { 4 entry: 5 %0 = zext i32 %a to i64 6 %1 = zext i32 %b to i64 7 %2 = mul i64 %1, %0 8 ret i64 %2 9 } 10 ; CHECK-LABEL: umul_lohi: 11 ; CHECK: ldc [[REG:r[0-9]+]], 0 12 ; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]] 13 ; CHECK-NEXT: retsp 0 14 15 define i64 @smul_lohi(i32 %a, i32 %b) { 16 entry: 17 %0 = sext i32 %a to i64 18 %1 = sext i32 %b to i64 19 %2 = mul i64 %1, %0 20 ret i64 %2 21 } 22 ; CHECK-LABEL: smul_lohi: 23 ; CHECK: ldc 24 ; CHECK-NEXT: mov 25 ; CHECK-NEXT: maccs 26 ; CHECK: retsp 0 27 28 define i64 @mul64(i64 %a, i64 %b) { 29 entry: 30 %0 = mul i64 %a, %b 31 ret i64 %0 32 } 33 ; CHECK-LABEL: mul64: 34 ; CHECK: ldc 35 ; CHECK-NEXT: lmul 36 ; CHECK-NEXT: mul 37 ; CHECK-NEXT: lmul 38 39 define i64 @mul64_2(i64 %a, i32 %b) { 40 entry: 41 %0 = zext i32 %b to i64 42 %1 = mul i64 %a, %0 43 ret i64 %1 44 } 45 ; CHECK-LABEL: mul64_2: 46 ; CHECK: ldc 47 ; CHECK-NEXT: lmul 48 ; CHECK-NEXT: mul 49 ; CHECK-NEXT: add r1, 50 ; CHECK: retsp 0 51
