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      1 # RUN: not llvm-mc -disassemble -triple=aarch64 %s 2> %t
      2 # RUN: FileCheck %s < %t
      3 # RUN: not llvm-mc -disassemble -triple=arm64 %s 2> %t
      4 # RUN: FileCheck %s < %t
      5 
      6 # Instructions notionally in the add/sub (extended register) sheet, but with
      7 # invalid shift amount or "opt" field.
      8 [0x00 0x10 0xa0 0x0b]
      9 [0x00 0x10 0x60 0x0b]
     10 [0x00 0x14 0x20 0x0b]
     11 # CHECK: invalid instruction encoding
     12 # CHECK: invalid instruction encoding
     13 # CHECK: invalid instruction encoding
     14 
     15 # Instructions notionally in the add/sub (immediate) sheet, but with
     16 # invalid "shift" field.
     17 [0xdf 0x3 0x80 0x91]
     18 [0xed 0x8e 0xc4 0x31]
     19 [0x62 0xfc 0xbf 0x11]
     20 [0x3 0xff 0xff 0x91]
     21 # CHECK: invalid instruction encoding
     22 # CHECK: invalid instruction encoding
     23 # CHECK: invalid instruction encoding
     24 # CHECK: invalid instruction encoding
     25 
     26 # Instructions notionally in the load/store (unsigned immediate) sheet.
     27 # Only unallocated (int-register) variants are: opc=0b11, size=0b10, 0b11
     28 [0xd7 0xfc 0xff 0xb9]
     29 [0xd7 0xfc 0xcf 0xf9]
     30 # CHECK: invalid instruction encoding
     31 # CHECK: invalid instruction encoding
     32 
     33 # Instructions notionally in the floating-point <-> fixed-point conversion
     34 # Scale field is 64-<imm> and <imm> should be 1-32 for a 32-bit int register.
     35 [0x23 0x01 0x18 0x1e]
     36 [0x23 0x25 0x42 0x1e]
     37 # CHECK: invalid instruction encoding
     38 # CHECK: invalid instruction encoding
     39 
     40 # Instructions notionally in the logical (shifted register) sheet, but with out
     41 # of range shift: w-registers can only have 0-31.
     42 [0x00 0x80 0x00 0x0a]
     43 # CHECK: invalid instruction encoding
     44 
     45 # Instructions notionally in the move wide (immediate) sheet, but with out
     46 # of range shift: w-registers can only have 0 or 16.
     47 [0x00 0x00 0xc0 0x12]
     48 [0x12 0x34 0xe0 0x52]
     49 # CHECK: invalid instruction encoding
     50 # CHECK: invalid instruction encoding
     51 
     52 # Data-processing instructions are undefined when S=1 and for the 0b0000111
     53 # value in opcode:sf
     54 [0x00 0x00 0xc0 0x5f]
     55 [0x56 0x0c 0xc0 0x5a]
     56 # CHECK: invalid instruction encoding
     57 # CHECK: invalid instruction encoding
     58 
     59 # Data-processing instructions (2 source) are undefined for a value of
     60 #  0001xx:0:x or 0011xx:0:x for opcode:S:sf
     61 [0x00 0x30 0xc1 0x1a]
     62 [0x00 0x10 0xc1 0x1a]
     63 # CHECK: invalid instruction encoding
     64 # CHECK: invalid instruction encoding
     65 
     66 
     67