1 ; REQUIRES: asserts 2 ; RUN: opt -loop-unswitch -loop-unswitch-threshold 1000 -disable-output -stats -info-output-file - < %s | FileCheck --check-prefix=STATS %s 3 ; RUN: opt -S -loop-unswitch -loop-unswitch-threshold 1000 -verify-loop-info -verify-dom-info < %s | FileCheck %s 4 5 ; STATS: 1 loop-simplify - Number of pre-header or exit blocks inserted 6 ; STATS: 3 loop-unswitch - Number of switches unswitched 7 8 ; CHECK: %1 = icmp eq i32 %c, 1 9 ; CHECK-NEXT: br i1 %1, label %.split.us, label %..split_crit_edge 10 11 ; CHECK: ..split_crit_edge: ; preds = %0 12 ; CHECK-NEXT: br label %.split 13 14 ; CHECK: .split.us: ; preds = %0 15 ; CHECK-NEXT: %2 = icmp eq i32 %d, 1 16 ; CHECK-NEXT: br i1 %2, label %.split.us.split.us, label %.split.us..split.us.split_crit_edge 17 18 ; CHECK: .split.us..split.us.split_crit_edge: ; preds = %.split.us 19 ; CHECK-NEXT: br label %.split.us.split 20 21 ; CHECK: .split.us.split.us: ; preds = %.split.us 22 ; CHECK-NEXT: br label %loop_begin.us.us 23 24 ; CHECK: loop_begin.us.us: ; preds = %loop_begin.backedge.us.us, %.split.us.split.us 25 ; CHECK-NEXT: %var_val.us.us = load i32* %var 26 ; CHECK-NEXT: switch i32 1, label %second_switch.us.us [ 27 ; CHECK-NEXT: i32 1, label %inc.us.us 28 29 ; CHECK: second_switch.us.us: ; preds = %loop_begin.us.us 30 ; CHECK-NEXT: switch i32 1, label %default.us.us [ 31 ; CHECK-NEXT: i32 1, label %inc.us.us 32 33 ; CHECK: inc.us.us: ; preds = %second_switch.us.us, %loop_begin.us.us 34 ; CHECK-NEXT: call void @incf() [[NOR_NUW:#[0-9]+]] 35 ; CHECK-NEXT: br label %loop_begin.backedge.us.us 36 37 ; CHECK: .split.us.split: ; preds = %.split.us..split.us.split_crit_edge 38 ; CHECK-NEXT: br label %loop_begin.us 39 40 ; CHECK: loop_begin.us: ; preds = %loop_begin.backedge.us, %.split.us.split 41 ; CHECK-NEXT: %var_val.us = load i32* %var 42 ; CHECK-NEXT: switch i32 1, label %second_switch.us [ 43 ; CHECK-NEXT: i32 1, label %inc.us 44 45 ; CHECK: second_switch.us: ; preds = %loop_begin.us 46 ; CHECK-NEXT: switch i32 %d, label %default.us [ 47 ; CHECK-NEXT: i32 1, label %second_switch.us.inc.us_crit_edge 48 ; CHECK-NEXT: ] 49 50 ; CHECK: second_switch.us.inc.us_crit_edge: ; preds = %second_switch.us 51 ; CHECK-NEXT: br i1 true, label %us-unreachable8, label %inc.us 52 53 ; CHECK: inc.us: ; preds = %second_switch.us.inc.us_crit_edge, %loop_begin.us 54 ; CHECK-NEXT: call void @incf() [[NOR_NUW]] 55 ; CHECK-NEXT: br label %loop_begin.backedge.us 56 57 ; CHECK: .split: ; preds = %..split_crit_edge 58 ; CHECK-NEXT: %3 = icmp eq i32 %d, 1 59 ; CHECK-NEXT: br i1 %3, label %.split.split.us, label %.split..split.split_crit_edge 60 61 ; CHECK: .split..split.split_crit_edge: ; preds = %.split 62 ; CHECK-NEXT: br label %.split.split 63 64 ; CHECK: .split.split.us: ; preds = %.split 65 ; CHECK-NEXT: br label %loop_begin.us1 66 67 ; CHECK: loop_begin.us1: ; preds = %loop_begin.backedge.us6, %.split.split.us 68 ; CHECK-NEXT: %var_val.us2 = load i32* %var 69 ; CHECK-NEXT: switch i32 %c, label %second_switch.us3 [ 70 ; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge.us 71 ; CHECK-NEXT: ] 72 73 ; CHECK: second_switch.us3: ; preds = %loop_begin.us1 74 ; CHECK-NEXT: switch i32 1, label %default.us5 [ 75 ; CHECK-NEXT: i32 1, label %inc.us4 76 ; CHECK-NEXT: ] 77 78 ; CHECK: inc.us4: ; preds = %loop_begin.inc_crit_edge.us, %second_switch.us3 79 ; CHECK-NEXT: call void @incf() [[NOR_NUW]] 80 ; CHECK-NEXT: br label %loop_begin.backedge.us6 81 82 ; CHECK: loop_begin.inc_crit_edge.us: ; preds = %loop_begin.us1 83 ; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa.us, label %inc.us4 84 85 ; CHECK: .split.split: ; preds = %.split..split.split_crit_edge 86 ; CHECK-NEXT: br label %loop_begin 87 88 ; CHECK: loop_begin: ; preds = %loop_begin.backedge, %.split.split 89 ; CHECK-NEXT: %var_val = load i32* %var 90 ; CHECK-NEXT: switch i32 %c, label %second_switch [ 91 ; CHECK-NEXT: i32 1, label %loop_begin.inc_crit_edge 92 ; CHECK-NEXT: ] 93 94 ; CHECK: loop_begin.inc_crit_edge: ; preds = %loop_begin 95 ; CHECK-NEXT: br i1 true, label %us-unreachable.us-lcssa, label %inc 96 97 ; CHECK: second_switch: ; preds = %loop_begin 98 ; CHECK-NEXT: switch i32 %d, label %default [ 99 ; CHECK-NEXT: i32 1, label %second_switch.inc_crit_edge 100 ; CHECK-NEXT: ] 101 102 ; CHECK: second_switch.inc_crit_edge: ; preds = %second_switch 103 ; CHECK-NEXT: br i1 true, label %us-unreachable7, label %inc 104 105 106 define i32 @test(i32* %var) { 107 %mem = alloca i32 108 store i32 2, i32* %mem 109 %c = load i32* %mem 110 %d = load i32* %mem 111 112 br label %loop_begin 113 114 loop_begin: 115 116 %var_val = load i32* %var 117 118 switch i32 %c, label %second_switch [ 119 i32 1, label %inc 120 ] 121 122 second_switch: 123 switch i32 %d, label %default [ 124 i32 1, label %inc 125 ] 126 127 inc: 128 call void @incf() noreturn nounwind 129 br label %loop_begin 130 131 default: 132 br label %loop_begin 133 134 loop_exit: 135 ret i32 0 136 } 137 138 declare void @incf() noreturn 139 declare void @decf() noreturn 140 141 ; CHECK: attributes #0 = { noreturn } 142 ; CHECK: attributes [[NOR_NUW]] = { noreturn nounwind } 143
