1 /* 2 * Copyright 2012 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric (at) anholt.net> 25 * 26 */ 27 28 #include "brw_fs_cfg.h" 29 #include "brw_fs_live_variables.h" 30 31 using namespace brw; 32 33 /** @file brw_fs_live_variables.cpp 34 * 35 * Support for computing at the basic block level which variables 36 * (virtual GRFs in our case) are live at entry and exit. 37 * 38 * See Muchnik's Advanced Compiler Design and Implementation, section 39 * 14.1 (p444). 40 */ 41 42 /** 43 * Sets up the use[] and def[] arrays. 44 * 45 * The basic-block-level live variable analysis needs to know which 46 * variables get used before they're completely defined, and which 47 * variables are completely defined before they're used. 48 */ 49 void 50 fs_live_variables::setup_def_use() 51 { 52 int ip = 0; 53 54 for (int b = 0; b < cfg->num_blocks; b++) { 55 fs_bblock *block = cfg->blocks[b]; 56 57 assert(ip == block->start_ip); 58 if (b > 0) 59 assert(cfg->blocks[b - 1]->end_ip == ip - 1); 60 61 for (fs_inst *inst = block->start; 62 inst != block->end->next; 63 inst = (fs_inst *)inst->next) { 64 65 /* Set use[] for this instruction */ 66 for (unsigned int i = 0; i < 3; i++) { 67 if (inst->src[i].file == GRF) { 68 int reg = inst->src[i].reg; 69 70 if (!bd[b].def[reg]) 71 bd[b].use[reg] = true; 72 } 73 } 74 75 /* Check for unconditional writes to whole registers. These 76 * are the things that screen off preceding definitions of a 77 * variable, and thus qualify for being in def[]. 78 */ 79 if (inst->dst.file == GRF && 80 inst->regs_written() == v->virtual_grf_sizes[inst->dst.reg] && 81 !inst->predicated && 82 !inst->force_uncompressed && 83 !inst->force_sechalf) { 84 int reg = inst->dst.reg; 85 if (!bd[b].use[reg]) 86 bd[b].def[reg] = true; 87 } 88 89 ip++; 90 } 91 } 92 } 93 94 /** 95 * The algorithm incrementally sets bits in liveout and livein, 96 * propagating it through control flow. It will eventually terminate 97 * because it only ever adds bits, and stops when no bits are added in 98 * a pass. 99 */ 100 void 101 fs_live_variables::compute_live_variables() 102 { 103 bool cont = true; 104 105 while (cont) { 106 cont = false; 107 108 for (int b = 0; b < cfg->num_blocks; b++) { 109 /* Update livein */ 110 for (int i = 0; i < num_vars; i++) { 111 if (bd[b].use[i] || (bd[b].liveout[i] && !bd[b].def[i])) { 112 if (!bd[b].livein[i]) { 113 bd[b].livein[i] = true; 114 cont = true; 115 } 116 } 117 } 118 119 /* Update liveout */ 120 foreach_list(block_node, &cfg->blocks[b]->children) { 121 fs_bblock_link *link = (fs_bblock_link *)block_node; 122 fs_bblock *block = link->block; 123 124 for (int i = 0; i < num_vars; i++) { 125 if (bd[block->block_num].livein[i] && !bd[b].liveout[i]) { 126 bd[b].liveout[i] = true; 127 cont = true; 128 } 129 } 130 } 131 } 132 } 133 } 134 135 fs_live_variables::fs_live_variables(fs_visitor *v, fs_cfg *cfg) 136 : v(v), cfg(cfg) 137 { 138 mem_ctx = ralloc_context(cfg->mem_ctx); 139 140 num_vars = v->virtual_grf_count; 141 bd = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks); 142 143 for (int i = 0; i < cfg->num_blocks; i++) { 144 bd[i].def = rzalloc_array(mem_ctx, bool, num_vars); 145 bd[i].use = rzalloc_array(mem_ctx, bool, num_vars); 146 bd[i].livein = rzalloc_array(mem_ctx, bool, num_vars); 147 bd[i].liveout = rzalloc_array(mem_ctx, bool, num_vars); 148 } 149 150 setup_def_use(); 151 compute_live_variables(); 152 } 153 154 fs_live_variables::~fs_live_variables() 155 { 156 ralloc_free(mem_ctx); 157 } 158 159 #define MAX_INSTRUCTION (1 << 30) 160 161 void 162 fs_visitor::calculate_live_intervals() 163 { 164 int num_vars = this->virtual_grf_count; 165 166 if (this->live_intervals_valid) 167 return; 168 169 int *def = ralloc_array(mem_ctx, int, num_vars); 170 int *use = ralloc_array(mem_ctx, int, num_vars); 171 ralloc_free(this->virtual_grf_def); 172 ralloc_free(this->virtual_grf_use); 173 this->virtual_grf_def = def; 174 this->virtual_grf_use = use; 175 176 for (int i = 0; i < num_vars; i++) { 177 def[i] = MAX_INSTRUCTION; 178 use[i] = -1; 179 } 180 181 /* Start by setting up the intervals with no knowledge of control 182 * flow. 183 */ 184 int ip = 0; 185 foreach_list(node, &this->instructions) { 186 fs_inst *inst = (fs_inst *)node; 187 188 for (unsigned int i = 0; i < 3; i++) { 189 if (inst->src[i].file == GRF) { 190 int reg = inst->src[i].reg; 191 192 use[reg] = ip; 193 } 194 } 195 196 if (inst->dst.file == GRF) { 197 int reg = inst->dst.reg; 198 199 def[reg] = MIN2(def[reg], ip); 200 } 201 202 ip++; 203 } 204 205 /* Now, extend those intervals using our analysis of control flow. */ 206 fs_cfg cfg(this); 207 fs_live_variables livevars(this, &cfg); 208 209 for (int b = 0; b < cfg.num_blocks; b++) { 210 for (int i = 0; i < num_vars; i++) { 211 if (livevars.bd[b].livein[i]) { 212 def[i] = MIN2(def[i], cfg.blocks[b]->start_ip); 213 use[i] = MAX2(use[i], cfg.blocks[b]->start_ip); 214 } 215 216 if (livevars.bd[b].liveout[i]) { 217 def[i] = MIN2(def[i], cfg.blocks[b]->end_ip); 218 use[i] = MAX2(use[i], cfg.blocks[b]->end_ip); 219 } 220 } 221 } 222 223 this->live_intervals_valid = true; 224 225 /* Note in the non-control-flow code above, that we only take def[] as the 226 * first store, and use[] as the last use. We use this in dead code 227 * elimination, to determine when a store never gets used. However, we 228 * also use these arrays to answer the virtual_grf_interferes() question 229 * (live interval analysis), which is used for register coalescing and 230 * register allocation. 231 * 232 * So, there's a conflict over what the array should mean: if use[] 233 * considers a def after the last use, then the dead code elimination pass 234 * never does anything (and it's an important pass!). But if we don't 235 * include dead code, then virtual_grf_interferes() lies and we'll do 236 * horrible things like coalesce the register that is dead-code-written 237 * into another register that was live across the dead write (causing the 238 * use of the second register to take the dead write's source value instead 239 * of the coalesced MOV's source value). 240 * 241 * To resolve the conflict, immediately after calculating live intervals, 242 * detect dead code, nuke it, and if we changed anything, calculate again 243 * before returning to the caller. Now we happen to produce def[] and 244 * use[] arrays that will work for virtual_grf_interferes(). 245 */ 246 if (dead_code_eliminate()) 247 calculate_live_intervals(); 248 } 249 250 bool 251 fs_visitor::virtual_grf_interferes(int a, int b) 252 { 253 int a_def = this->virtual_grf_def[a], a_use = this->virtual_grf_use[a]; 254 int b_def = this->virtual_grf_def[b], b_use = this->virtual_grf_use[b]; 255 256 /* If there's dead code (def but not use), it would break our test 257 * unless we consider it used. 258 */ 259 if ((a_use == -1 && a_def != MAX_INSTRUCTION) || 260 (b_use == -1 && b_def != MAX_INSTRUCTION)) { 261 return true; 262 } 263 264 int start = MAX2(a_def, b_def); 265 int end = MIN2(a_use, b_use); 266 267 /* If the register is used to store 16 values of less than float 268 * size (only the case for pixel_[xy]), then we can't allocate 269 * another dword-sized thing to that register that would be used in 270 * the same instruction. This is because when the GPU decodes (for 271 * example): 272 * 273 * (declare (in ) vec4 gl_FragCoord@0x97766a0) 274 * add(16) g6<1>F g6<8,8,1>UW 0.5F { align1 compr }; 275 * 276 * it's actually processed as: 277 * add(8) g6<1>F g6<8,8,1>UW 0.5F { align1 }; 278 * add(8) g7<1>F g6.8<8,8,1>UW 0.5F { align1 sechalf }; 279 * 280 * so our second half values in g6 got overwritten in the first 281 * half. 282 */ 283 if (c->dispatch_width == 16 && (this->pixel_x.reg == a || 284 this->pixel_x.reg == b || 285 this->pixel_y.reg == a || 286 this->pixel_y.reg == b)) { 287 return start <= end; 288 } 289 290 return start < end; 291 } 292
