Home | History | Annotate | Download | only in intc
      1 /*
      2  *  ioapic.c IOAPIC emulation logic
      3  *
      4  *  Copyright (c) 2004-2005 Fabrice Bellard
      5  *
      6  *  Split the ioapic logic from apic.c
      7  *  Xiantao Zhang <xiantao.zhang (at) intel.com>
      8  *
      9  * This library is free software; you can redistribute it and/or
     10  * modify it under the terms of the GNU Lesser General Public
     11  * License as published by the Free Software Foundation; either
     12  * version 2 of the License, or (at your option) any later version.
     13  *
     14  * This library is distributed in the hope that it will be useful,
     15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
     16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
     17  * Lesser General Public License for more details.
     18  *
     19  * You should have received a copy of the GNU Lesser General Public
     20  * License along with this library; if not, write to the Free Software
     21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
     22  */
     23 
     24 #include "hw/hw.h"
     25 #include "hw/i386/pc.h"
     26 #include "qemu/timer.h"
     27 #include "qemu/host-utils.h"
     28 
     29 //#define DEBUG_IOAPIC
     30 
     31 #define IOAPIC_NUM_PINS			0x18
     32 #define IOAPIC_LVT_MASKED 		(1<<16)
     33 
     34 #define IOAPIC_TRIGGER_EDGE		0
     35 #define IOAPIC_TRIGGER_LEVEL		1
     36 
     37 /*io{apic,sapic} delivery mode*/
     38 #define IOAPIC_DM_FIXED			0x0
     39 #define IOAPIC_DM_LOWEST_PRIORITY	0x1
     40 #define IOAPIC_DM_PMI			0x2
     41 #define IOAPIC_DM_NMI			0x4
     42 #define IOAPIC_DM_INIT			0x5
     43 #define IOAPIC_DM_SIPI			0x5
     44 #define IOAPIC_DM_EXTINT		0x7
     45 
     46 struct IOAPICState {
     47     uint8_t id;
     48     uint8_t ioregsel;
     49 
     50     uint32_t irr;
     51     uint64_t ioredtbl[IOAPIC_NUM_PINS];
     52 };
     53 
     54 static void ioapic_service(IOAPICState *s)
     55 {
     56     uint8_t i;
     57     uint8_t trig_mode;
     58     uint8_t vector;
     59     uint8_t delivery_mode;
     60     uint32_t mask;
     61     uint64_t entry;
     62     uint8_t dest;
     63     uint8_t dest_mode;
     64     uint8_t polarity;
     65 
     66     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
     67         mask = 1 << i;
     68         if (s->irr & mask) {
     69             entry = s->ioredtbl[i];
     70             if (!(entry & IOAPIC_LVT_MASKED)) {
     71                 trig_mode = ((entry >> 15) & 1);
     72                 dest = entry >> 56;
     73                 dest_mode = (entry >> 11) & 1;
     74                 delivery_mode = (entry >> 8) & 7;
     75                 polarity = (entry >> 13) & 1;
     76                 if (trig_mode == IOAPIC_TRIGGER_EDGE)
     77                     s->irr &= ~mask;
     78                 if (delivery_mode == IOAPIC_DM_EXTINT)
     79                     vector = pic_read_irq(isa_pic);
     80                 else
     81                     vector = entry & 0xff;
     82 
     83                 apic_deliver_irq(dest, dest_mode, delivery_mode,
     84                                  vector, polarity, trig_mode);
     85             }
     86         }
     87     }
     88 }
     89 
     90 void ioapic_set_irq(void *opaque, int vector, int level)
     91 {
     92     IOAPICState *s = opaque;
     93 
     94     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
     95      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
     96      * the cleanest way of doing it but it should work. */
     97 
     98     if (vector == 0)
     99         vector = 2;
    100 
    101     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
    102         uint32_t mask = 1 << vector;
    103         uint64_t entry = s->ioredtbl[vector];
    104 
    105         if ((entry >> 15) & 1) {
    106             /* level triggered */
    107             if (level) {
    108                 s->irr |= mask;
    109                 ioapic_service(s);
    110             } else {
    111                 s->irr &= ~mask;
    112             }
    113         } else {
    114             /* edge triggered */
    115             if (level) {
    116                 s->irr |= mask;
    117                 ioapic_service(s);
    118             }
    119         }
    120     }
    121 }
    122 
    123 static uint32_t ioapic_mem_readl(void *opaque, hwaddr addr)
    124 {
    125     IOAPICState *s = opaque;
    126     int index;
    127     uint32_t val = 0;
    128 
    129     addr &= 0xff;
    130     if (addr == 0x00) {
    131         val = s->ioregsel;
    132     } else if (addr == 0x10) {
    133         switch (s->ioregsel) {
    134             case 0x00:
    135                 val = s->id << 24;
    136                 break;
    137             case 0x01:
    138                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
    139                 break;
    140             case 0x02:
    141                 val = 0;
    142                 break;
    143             default:
    144                 index = (s->ioregsel - 0x10) >> 1;
    145                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
    146                     if (s->ioregsel & 1)
    147                         val = s->ioredtbl[index] >> 32;
    148                     else
    149                         val = s->ioredtbl[index] & 0xffffffff;
    150                 }
    151         }
    152 #ifdef DEBUG_IOAPIC
    153         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
    154 #endif
    155     }
    156     return val;
    157 }
    158 
    159 static void ioapic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
    160 {
    161     IOAPICState *s = opaque;
    162     int index;
    163 
    164     addr &= 0xff;
    165     if (addr == 0x00)  {
    166         s->ioregsel = val;
    167         return;
    168     } else if (addr == 0x10) {
    169 #ifdef DEBUG_IOAPIC
    170         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
    171 #endif
    172         switch (s->ioregsel) {
    173             case 0x00:
    174                 s->id = (val >> 24) & 0xff;
    175                 return;
    176             case 0x01:
    177             case 0x02:
    178                 return;
    179             default:
    180                 index = (s->ioregsel - 0x10) >> 1;
    181                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
    182                     if (s->ioregsel & 1) {
    183                         s->ioredtbl[index] &= 0xffffffff;
    184                         s->ioredtbl[index] |= (uint64_t)val << 32;
    185                     } else {
    186                         s->ioredtbl[index] &= ~0xffffffffULL;
    187                         s->ioredtbl[index] |= val;
    188                     }
    189                     ioapic_service(s);
    190                 }
    191         }
    192     }
    193 }
    194 
    195 static void ioapic_save(QEMUFile *f, void *opaque)
    196 {
    197     IOAPICState *s = opaque;
    198     int i;
    199 
    200     qemu_put_8s(f, &s->id);
    201     qemu_put_8s(f, &s->ioregsel);
    202     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
    203         qemu_put_be64s(f, &s->ioredtbl[i]);
    204     }
    205 }
    206 
    207 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
    208 {
    209     IOAPICState *s = opaque;
    210     int i;
    211 
    212     if (version_id != 1)
    213         return -EINVAL;
    214 
    215     qemu_get_8s(f, &s->id);
    216     qemu_get_8s(f, &s->ioregsel);
    217     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
    218         qemu_get_be64s(f, &s->ioredtbl[i]);
    219     }
    220     return 0;
    221 }
    222 
    223 static void ioapic_reset(void *opaque)
    224 {
    225     IOAPICState *s = opaque;
    226     int i;
    227 
    228     memset(s, 0, sizeof(*s));
    229     for(i = 0; i < IOAPIC_NUM_PINS; i++)
    230         s->ioredtbl[i] = 1 << 16; /* mask LVT */
    231 }
    232 
    233 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
    234     ioapic_mem_readl,
    235     ioapic_mem_readl,
    236     ioapic_mem_readl,
    237 };
    238 
    239 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
    240     ioapic_mem_writel,
    241     ioapic_mem_writel,
    242     ioapic_mem_writel,
    243 };
    244 
    245 IOAPICState *ioapic_init(void)
    246 {
    247     IOAPICState *s;
    248     int io_memory;
    249 
    250     s = g_malloc0(sizeof(IOAPICState));
    251     ioapic_reset(s);
    252 
    253     io_memory = cpu_register_io_memory(ioapic_mem_read,
    254                                        ioapic_mem_write, s);
    255     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
    256 
    257     register_savevm(NULL, "ioapic", 0, 1, ioapic_save, ioapic_load, s);
    258     qemu_register_reset(ioapic_reset, 0, s);
    259 
    260     return s;
    261 }
    262