1 2 /*---------------------------------------------------------------*/ 3 /*--- begin host_ppc_defs.h ---*/ 4 /*---------------------------------------------------------------*/ 5 6 /* 7 This file is part of Valgrind, a dynamic binary instrumentation 8 framework. 9 10 Copyright (C) 2004-2013 OpenWorks LLP 11 info (at) open-works.net 12 13 This program is free software; you can redistribute it and/or 14 modify it under the terms of the GNU General Public License as 15 published by the Free Software Foundation; either version 2 of the 16 License, or (at your option) any later version. 17 18 This program is distributed in the hope that it will be useful, but 19 WITHOUT ANY WARRANTY; without even the implied warranty of 20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 21 General Public License for more details. 22 23 You should have received a copy of the GNU General Public License 24 along with this program; if not, write to the Free Software 25 Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 26 02110-1301, USA. 27 28 The GNU General Public License is contained in the file COPYING. 29 30 Neither the names of the U.S. Department of Energy nor the 31 University of California nor the names of its contributors may be 32 used to endorse or promote products derived from this software 33 without prior written permission. 34 */ 35 36 #ifndef __VEX_HOST_PPC_DEFS_H 37 #define __VEX_HOST_PPC_DEFS_H 38 39 #include "libvex_basictypes.h" 40 #include "libvex.h" // VexArch 41 #include "host_generic_regs.h" // HReg 42 43 /* Num registers used for function calls */ 44 #define PPC_N_REGPARMS 8 45 46 47 /* --------- Registers. --------- */ 48 49 /* The usual HReg abstraction. There are 32 real int regs, 50 32 real float regs, and 32 real vector regs. 51 */ 52 53 extern void ppHRegPPC ( HReg ); 54 55 extern HReg hregPPC_GPR0 ( Bool mode64 ); // scratch reg / zero reg 56 extern HReg hregPPC_GPR1 ( Bool mode64 ); // Stack Frame Pointer 57 extern HReg hregPPC_GPR2 ( Bool mode64 ); // not used: TOC pointer 58 extern HReg hregPPC_GPR3 ( Bool mode64 ); 59 extern HReg hregPPC_GPR4 ( Bool mode64 ); 60 extern HReg hregPPC_GPR5 ( Bool mode64 ); 61 extern HReg hregPPC_GPR6 ( Bool mode64 ); 62 extern HReg hregPPC_GPR7 ( Bool mode64 ); 63 extern HReg hregPPC_GPR8 ( Bool mode64 ); 64 extern HReg hregPPC_GPR9 ( Bool mode64 ); 65 extern HReg hregPPC_GPR10 ( Bool mode64 ); 66 extern HReg hregPPC_GPR11 ( Bool mode64 ); 67 extern HReg hregPPC_GPR12 ( Bool mode64 ); 68 extern HReg hregPPC_GPR13 ( Bool mode64 ); 69 extern HReg hregPPC_GPR14 ( Bool mode64 ); 70 extern HReg hregPPC_GPR15 ( Bool mode64 ); 71 extern HReg hregPPC_GPR16 ( Bool mode64 ); 72 extern HReg hregPPC_GPR17 ( Bool mode64 ); 73 extern HReg hregPPC_GPR18 ( Bool mode64 ); 74 extern HReg hregPPC_GPR19 ( Bool mode64 ); 75 extern HReg hregPPC_GPR20 ( Bool mode64 ); 76 extern HReg hregPPC_GPR21 ( Bool mode64 ); 77 extern HReg hregPPC_GPR22 ( Bool mode64 ); 78 extern HReg hregPPC_GPR23 ( Bool mode64 ); 79 extern HReg hregPPC_GPR24 ( Bool mode64 ); 80 extern HReg hregPPC_GPR25 ( Bool mode64 ); 81 extern HReg hregPPC_GPR26 ( Bool mode64 ); 82 extern HReg hregPPC_GPR27 ( Bool mode64 ); 83 extern HReg hregPPC_GPR28 ( Bool mode64 ); 84 extern HReg hregPPC_GPR29 ( Bool mode64 ); // reserved for dispatcher 85 extern HReg hregPPC_GPR30 ( Bool mode64 ); // used as VMX spill temp 86 extern HReg hregPPC_GPR31 ( Bool mode64 ); // GuestStatePtr (callee-saved) 87 88 extern HReg hregPPC_FPR0 ( void ); 89 extern HReg hregPPC_FPR1 ( void ); 90 extern HReg hregPPC_FPR2 ( void ); 91 extern HReg hregPPC_FPR3 ( void ); 92 extern HReg hregPPC_FPR4 ( void ); 93 extern HReg hregPPC_FPR5 ( void ); 94 extern HReg hregPPC_FPR6 ( void ); 95 extern HReg hregPPC_FPR7 ( void ); 96 extern HReg hregPPC_FPR8 ( void ); 97 extern HReg hregPPC_FPR9 ( void ); 98 extern HReg hregPPC_FPR10 ( void ); 99 extern HReg hregPPC_FPR11 ( void ); 100 extern HReg hregPPC_FPR12 ( void ); 101 extern HReg hregPPC_FPR13 ( void ); 102 extern HReg hregPPC_FPR14 ( void ); 103 extern HReg hregPPC_FPR15 ( void ); 104 extern HReg hregPPC_FPR16 ( void ); 105 extern HReg hregPPC_FPR17 ( void ); 106 extern HReg hregPPC_FPR18 ( void ); 107 extern HReg hregPPC_FPR19 ( void ); 108 extern HReg hregPPC_FPR20 ( void ); 109 extern HReg hregPPC_FPR21 ( void ); 110 extern HReg hregPPC_FPR22 ( void ); 111 extern HReg hregPPC_FPR23 ( void ); 112 extern HReg hregPPC_FPR24 ( void ); 113 extern HReg hregPPC_FPR25 ( void ); 114 extern HReg hregPPC_FPR26 ( void ); 115 extern HReg hregPPC_FPR27 ( void ); 116 extern HReg hregPPC_FPR28 ( void ); 117 extern HReg hregPPC_FPR29 ( void ); 118 extern HReg hregPPC_FPR30 ( void ); 119 extern HReg hregPPC_FPR31 ( void ); 120 121 extern HReg hregPPC_VR0 ( void ); 122 extern HReg hregPPC_VR1 ( void ); 123 extern HReg hregPPC_VR2 ( void ); 124 extern HReg hregPPC_VR3 ( void ); 125 extern HReg hregPPC_VR4 ( void ); 126 extern HReg hregPPC_VR5 ( void ); 127 extern HReg hregPPC_VR6 ( void ); 128 extern HReg hregPPC_VR7 ( void ); 129 extern HReg hregPPC_VR8 ( void ); 130 extern HReg hregPPC_VR9 ( void ); 131 extern HReg hregPPC_VR10 ( void ); 132 extern HReg hregPPC_VR11 ( void ); 133 extern HReg hregPPC_VR12 ( void ); 134 extern HReg hregPPC_VR13 ( void ); 135 extern HReg hregPPC_VR14 ( void ); 136 extern HReg hregPPC_VR15 ( void ); 137 extern HReg hregPPC_VR16 ( void ); 138 extern HReg hregPPC_VR17 ( void ); 139 extern HReg hregPPC_VR18 ( void ); 140 extern HReg hregPPC_VR19 ( void ); 141 extern HReg hregPPC_VR20 ( void ); 142 extern HReg hregPPC_VR21 ( void ); 143 extern HReg hregPPC_VR22 ( void ); 144 extern HReg hregPPC_VR23 ( void ); 145 extern HReg hregPPC_VR24 ( void ); 146 extern HReg hregPPC_VR25 ( void ); 147 extern HReg hregPPC_VR26 ( void ); 148 extern HReg hregPPC_VR27 ( void ); 149 extern HReg hregPPC_VR28 ( void ); 150 extern HReg hregPPC_VR29 ( void ); 151 extern HReg hregPPC_VR30 ( void ); 152 extern HReg hregPPC_VR31 ( void ); 153 154 #define StackFramePtr(_mode64) hregPPC_GPR1(_mode64) 155 #define GuestStatePtr(_mode64) hregPPC_GPR31(_mode64) 156 157 158 159 /* --------- Condition codes --------- */ 160 161 /* This gives names from bitfields in CR; hence it names BI numbers */ 162 /* Using IBM/hardware indexing convention */ 163 typedef 164 enum { 165 // CR7, which we use for integer compares 166 Pcf_7LT = 28, /* neg | lt */ 167 Pcf_7GT = 29, /* pos | gt */ 168 Pcf_7EQ = 30, /* zero | equal */ 169 Pcf_7SO = 31, /* summary overflow */ 170 Pcf_NONE = 32 /* no condition; used with Pct_ALWAYS */ 171 } 172 PPCCondFlag; 173 174 typedef 175 enum { /* Maps bc bitfield BO */ 176 Pct_FALSE = 0x4, /* associated PPCCondFlag must not be Pcf_NONE */ 177 Pct_TRUE = 0xC, /* associated PPCCondFlag must not be Pcf_NONE */ 178 Pct_ALWAYS = 0x14 /* associated PPCCondFlag must be Pcf_NONE */ 179 } 180 PPCCondTest; 181 182 typedef 183 struct { 184 PPCCondFlag flag; 185 PPCCondTest test; 186 } 187 PPCCondCode; 188 189 extern const HChar* showPPCCondCode ( PPCCondCode ); 190 191 /* constructor */ 192 extern PPCCondCode mk_PPCCondCode ( PPCCondTest, PPCCondFlag ); 193 194 /* false->true, true->false */ 195 extern PPCCondTest invertCondTest ( PPCCondTest ); 196 197 198 199 200 /* --------- Memory address expressions (amodes). --------- */ 201 202 typedef 203 enum { 204 Pam_IR=1, /* Immediate (signed 16-bit) + Reg */ 205 Pam_RR=2 /* Reg1 + Reg2 */ 206 } 207 PPCAModeTag; 208 209 typedef 210 struct { 211 PPCAModeTag tag; 212 union { 213 struct { 214 HReg base; 215 Int index; 216 } IR; 217 struct { 218 HReg base; 219 HReg index; 220 } RR; 221 } Pam; 222 } 223 PPCAMode; 224 225 extern PPCAMode* PPCAMode_IR ( Int, HReg ); 226 extern PPCAMode* PPCAMode_RR ( HReg, HReg ); 227 228 extern PPCAMode* dopyPPCAMode ( PPCAMode* ); 229 230 extern void ppPPCAMode ( PPCAMode* ); 231 232 233 /* --------- Operand, which can be a reg or a u16/s16. --------- */ 234 /* ("RH" == "Register or Halfword immediate") */ 235 typedef 236 enum { 237 Prh_Imm=3, 238 Prh_Reg=4 239 } 240 PPCRHTag; 241 242 typedef 243 struct { 244 PPCRHTag tag; 245 union { 246 struct { 247 Bool syned; 248 UShort imm16; 249 } Imm; 250 struct { 251 HReg reg; 252 } Reg; 253 } 254 Prh; 255 } 256 PPCRH; 257 258 extern PPCRH* PPCRH_Imm ( Bool, UShort ); 259 extern PPCRH* PPCRH_Reg ( HReg ); 260 261 extern void ppPPCRH ( PPCRH* ); 262 263 264 /* --------- Operand, which can be a reg or a u32/64. --------- */ 265 266 typedef 267 enum { 268 Pri_Imm=5, 269 Pri_Reg=6 270 } 271 PPCRITag; 272 273 typedef 274 struct { 275 PPCRITag tag; 276 union { 277 ULong Imm; 278 HReg Reg; 279 } 280 Pri; 281 } 282 PPCRI; 283 284 extern PPCRI* PPCRI_Imm ( ULong ); 285 extern PPCRI* PPCRI_Reg( HReg ); 286 287 extern void ppPPCRI ( PPCRI* ); 288 289 290 /* --------- Operand, which can be a vector reg or a s6. --------- */ 291 /* ("VI" == "Vector Register or Immediate") */ 292 typedef 293 enum { 294 Pvi_Imm=7, 295 Pvi_Reg=8 296 } 297 PPCVI5sTag; 298 299 typedef 300 struct { 301 PPCVI5sTag tag; 302 union { 303 Char Imm5s; 304 HReg Reg; 305 } 306 Pvi; 307 } 308 PPCVI5s; 309 310 extern PPCVI5s* PPCVI5s_Imm ( Char ); 311 extern PPCVI5s* PPCVI5s_Reg ( HReg ); 312 313 extern void ppPPCVI5s ( PPCVI5s* ); 314 315 316 /* --------- Instructions. --------- */ 317 318 /* --------- */ 319 typedef 320 enum { 321 Pun_NEG, 322 Pun_NOT, 323 Pun_CLZ32, 324 Pun_CLZ64, 325 Pun_EXTSW 326 } 327 PPCUnaryOp; 328 329 extern const HChar* showPPCUnaryOp ( PPCUnaryOp ); 330 331 332 /* --------- */ 333 typedef 334 enum { 335 Palu_INVALID, 336 Palu_ADD, Palu_SUB, 337 Palu_AND, Palu_OR, Palu_XOR, 338 } 339 PPCAluOp; 340 341 extern 342 const HChar* showPPCAluOp ( PPCAluOp, 343 Bool /* is the 2nd operand an immediate? */); 344 345 346 /* --------- */ 347 typedef 348 enum { 349 Pshft_INVALID, 350 Pshft_SHL, Pshft_SHR, Pshft_SAR, 351 } 352 PPCShftOp; 353 354 extern 355 const HChar* showPPCShftOp ( PPCShftOp, 356 Bool /* is the 2nd operand an immediate? */, 357 Bool /* is this a 32bit or 64bit op? */ ); 358 359 360 /* --------- */ 361 typedef 362 enum { 363 Pfp_INVALID, 364 365 /* Ternary */ 366 Pfp_MADDD, Pfp_MSUBD, 367 Pfp_MADDS, Pfp_MSUBS, 368 Pfp_DFPADD, Pfp_DFPADDQ, 369 Pfp_DFPSUB, Pfp_DFPSUBQ, 370 Pfp_DFPMUL, Pfp_DFPMULQ, 371 Pfp_DFPDIV, Pfp_DFPDIVQ, 372 Pfp_DQUAQ, Pfp_DRRNDQ, 373 374 /* Binary */ 375 Pfp_ADDD, Pfp_SUBD, Pfp_MULD, Pfp_DIVD, 376 Pfp_ADDS, Pfp_SUBS, Pfp_MULS, Pfp_DIVS, 377 Pfp_DRSP, Pfp_DRDPQ, Pfp_DCTFIX, Pfp_DCTFIXQ, Pfp_DCFFIX, 378 Pfp_DQUA, Pfp_RRDTR, Pfp_DIEX, Pfp_DIEXQ, Pfp_DRINTN, 379 380 /* Unary */ 381 Pfp_SQRT, Pfp_ABS, Pfp_NEG, Pfp_MOV, Pfp_RES, Pfp_RSQRTE, 382 Pfp_FRIN, Pfp_FRIM, Pfp_FRIP, Pfp_FRIZ, 383 Pfp_DSCLI, Pfp_DSCRI, Pfp_DSCLIQ, Pfp_DSCRIQ, Pfp_DCTDP, 384 Pfp_DCTQPQ, Pfp_DCFFIXQ, Pfp_DXEX, Pfp_DXEXQ, 385 386 } 387 PPCFpOp; 388 389 extern const HChar* showPPCFpOp ( PPCFpOp ); 390 391 392 /* --------- */ 393 typedef 394 enum { 395 Pav_INVALID, 396 397 /* Integer Unary */ 398 Pav_MOV, /* Mov */ 399 Pav_NOT, /* Bitwise */ 400 Pav_UNPCKH8S, Pav_UNPCKH16S, /* Unpack */ 401 Pav_UNPCKL8S, Pav_UNPCKL16S, 402 Pav_UNPCKHPIX, Pav_UNPCKLPIX, 403 404 /* Integer Binary */ 405 Pav_AND, Pav_OR, Pav_XOR, /* Bitwise */ 406 Pav_ADDU, Pav_QADDU, Pav_QADDS, 407 Pav_SUBU, Pav_QSUBU, Pav_QSUBS, 408 Pav_MULU, 409 Pav_OMULU, Pav_OMULS, Pav_EMULU, Pav_EMULS, 410 Pav_AVGU, Pav_AVGS, 411 Pav_MAXU, Pav_MAXS, 412 Pav_MINU, Pav_MINS, 413 414 /* Compare (always affects CR field 6) */ 415 Pav_CMPEQU, Pav_CMPGTU, Pav_CMPGTS, 416 417 /* Shift */ 418 Pav_SHL, Pav_SHR, Pav_SAR, Pav_ROTL, 419 420 /* Pack */ 421 Pav_PACKUU, Pav_QPACKUU, Pav_QPACKSU, Pav_QPACKSS, 422 Pav_PACKPXL, 423 424 /* Merge */ 425 Pav_MRGHI, Pav_MRGLO, 426 427 /* Concatenation */ 428 Pav_CATODD, Pav_CATEVEN, 429 430 /* Polynomial Multipy-Add */ 431 Pav_POLYMULADD, 432 433 /* Cipher */ 434 Pav_CIPHERV128, Pav_CIPHERLV128, Pav_NCIPHERV128, Pav_NCIPHERLV128, 435 Pav_CIPHERSUBV128, 436 437 /* Hash */ 438 Pav_SHA256, Pav_SHA512, 439 440 /* BCD Arithmetic */ 441 Pav_BCDAdd, Pav_BCDSub, 442 443 /* zero count */ 444 Pav_ZEROCNTBYTE, Pav_ZEROCNTWORD, Pav_ZEROCNTHALF, Pav_ZEROCNTDBL, 445 446 /* Vector bit matrix transpose by byte */ 447 Pav_BITMTXXPOSE, 448 } 449 PPCAvOp; 450 451 extern const HChar* showPPCAvOp ( PPCAvOp ); 452 453 454 /* --------- */ 455 typedef 456 enum { 457 Pavfp_INVALID, 458 459 /* Floating point binary */ 460 Pavfp_ADDF, Pavfp_SUBF, Pavfp_MULF, 461 Pavfp_MAXF, Pavfp_MINF, 462 Pavfp_CMPEQF, Pavfp_CMPGTF, Pavfp_CMPGEF, 463 464 /* Floating point unary */ 465 Pavfp_RCPF, Pavfp_RSQRTF, 466 Pavfp_CVTU2F, Pavfp_CVTS2F, Pavfp_QCVTF2U, Pavfp_QCVTF2S, 467 Pavfp_ROUNDM, Pavfp_ROUNDP, Pavfp_ROUNDN, Pavfp_ROUNDZ, 468 } 469 PPCAvFpOp; 470 471 extern const HChar* showPPCAvFpOp ( PPCAvFpOp ); 472 473 474 /* --------- */ 475 typedef 476 enum { 477 Pin_LI, /* load word (32/64-bit) immediate (fake insn) */ 478 Pin_Alu, /* word add/sub/and/or/xor */ 479 Pin_Shft, /* word shl/shr/sar */ 480 Pin_AddSubC, /* add/sub with read/write carry */ 481 Pin_Cmp, /* word compare */ 482 Pin_Unary, /* not, neg, clz */ 483 Pin_MulL, /* widening multiply */ 484 Pin_Div, /* div */ 485 Pin_Call, /* call to address in register */ 486 Pin_XDirect, /* direct transfer to GA */ 487 Pin_XIndir, /* indirect transfer to GA */ 488 Pin_XAssisted, /* assisted transfer to GA */ 489 Pin_CMov, /* conditional move */ 490 Pin_Load, /* zero-extending load a 8|16|32|64 bit value from mem */ 491 Pin_LoadL, /* load-linked (lwarx/ldarx) 32|64 bit value from mem */ 492 Pin_Store, /* store a 8|16|32|64 bit value to mem */ 493 Pin_StoreC, /* store-conditional (stwcx./stdcx.) 32|64 bit val */ 494 Pin_Set, /* convert condition code to value 0 or 1 */ 495 Pin_MfCR, /* move from condition register to GPR */ 496 Pin_MFence, /* mem fence */ 497 498 Pin_FpUnary, /* FP unary op */ 499 Pin_FpBinary, /* FP binary op */ 500 Pin_FpMulAcc, /* FP multipy-accumulate style op */ 501 Pin_FpLdSt, /* FP load/store */ 502 Pin_FpSTFIW, /* stfiwx */ 503 Pin_FpRSP, /* FP round IEEE754 double to IEEE754 single */ 504 Pin_FpCftI, /* fcfid[u,s,us]/fctid[u]/fctiw[u] */ 505 Pin_FpCMov, /* FP floating point conditional move */ 506 Pin_FpLdFPSCR, /* mtfsf */ 507 Pin_FpCmp, /* FP compare, generating value into int reg */ 508 509 Pin_RdWrLR, /* Read/Write Link Register */ 510 511 Pin_AvLdSt, /* AV load/store (kludging for AMode_IR) */ 512 Pin_AvUnary, /* AV unary general reg=>reg */ 513 514 Pin_AvBinary, /* AV binary general reg,reg=>reg */ 515 Pin_AvBin8x16, /* AV binary, 8x4 */ 516 Pin_AvBin16x8, /* AV binary, 16x4 */ 517 Pin_AvBin32x4, /* AV binary, 32x4 */ 518 Pin_AvBin64x2, /* AV binary, 64x2 */ 519 520 Pin_AvBin32Fx4, /* AV FP binary, 32Fx4 */ 521 Pin_AvUn32Fx4, /* AV FP unary, 32Fx4 */ 522 523 Pin_AvPerm, /* AV permute (shuffle) */ 524 Pin_AvSel, /* AV select */ 525 Pin_AvShlDbl, /* AV shift-left double by imm */ 526 Pin_AvSplat, /* One elem repeated throughout dst */ 527 Pin_AvLdVSCR, /* mtvscr */ 528 Pin_AvCMov, /* AV conditional move */ 529 Pin_AvCipherV128Unary, /* AV Vector unary Cipher */ 530 Pin_AvCipherV128Binary, /* AV Vector binary Cipher */ 531 Pin_AvHashV128Binary, /* AV Vector binary Hash */ 532 Pin_AvBCDV128Trinary, /* BCD Arithmetic */ 533 Pin_Dfp64Unary, /* DFP64 unary op */ 534 Pin_Dfp128Unary, /* DFP128 unary op */ 535 Pin_DfpShift, /* Decimal floating point shift by immediate value */ 536 Pin_Dfp64Binary, /* DFP64 binary op */ 537 Pin_Dfp128Binary, /* DFP128 binary op */ 538 Pin_DfpShift128, /* 128-bit Decimal floating point shift by 539 * immediate value */ 540 Pin_DfpD128toD64, /* DFP 128 to DFP 64 op */ 541 Pin_DfpI64StoD128, /* DFP signed integer to DFP 128 */ 542 Pin_DfpRound, /* D64 round to D64 */ 543 Pin_DfpRound128, /* D128 round to D128 */ 544 Pin_ExtractExpD128, /* DFP, extract 64 bit exponent */ 545 Pin_InsertExpD128, /* DFP, insert 64 bit exponent and 128 bit binary 546 * significand into a DFP 128-bit value*/ 547 Pin_Dfp64Cmp, /* DFP 64-bit compare, generating value into 548 * int reg */ 549 Pin_Dfp128Cmp, /* DFP 128-bit compare, generating value into 550 * int reg */ 551 Pin_DfpQuantize, /* D64 quantize using register value, significance 552 * round */ 553 Pin_DfpQuantize128, /* D128 quantize using register value, significance 554 * round */ 555 Pin_EvCheck, /* Event check */ 556 Pin_ProfInc /* 64-bit profile counter increment */ 557 } 558 PPCInstrTag; 559 560 /* Destinations are on the LEFT (first operand) */ 561 562 typedef 563 struct { 564 PPCInstrTag tag; 565 union { 566 /* Get a 32/64-bit literal into a register. 567 May turn into a number of real insns. */ 568 struct { 569 HReg dst; 570 ULong imm64; 571 } LI; 572 /* Integer add/sub/and/or/xor. Limitations: 573 - For add, the immediate, if it exists, is a signed 16. 574 - For sub, the immediate, if it exists, is a signed 16 575 which may not be -32768, since no such instruction 576 exists, and so we have to emit addi with +32768, but 577 that is not possible. 578 - For and/or/xor, the immediate, if it exists, 579 is an unsigned 16. 580 */ 581 struct { 582 PPCAluOp op; 583 HReg dst; 584 HReg srcL; 585 PPCRH* srcR; 586 } Alu; 587 /* Integer shl/shr/sar. 588 Limitations: the immediate, if it exists, 589 is a signed 5-bit value between 1 and 31 inclusive. 590 */ 591 struct { 592 PPCShftOp op; 593 Bool sz32; /* mode64 has both 32 and 64bit shft */ 594 HReg dst; 595 HReg srcL; 596 PPCRH* srcR; 597 } Shft; 598 /* */ 599 struct { 600 Bool isAdd; /* else sub */ 601 Bool setC; /* else read carry */ 602 HReg dst; 603 HReg srcL; 604 HReg srcR; 605 } AddSubC; 606 /* If signed, the immediate, if it exists, is a signed 16, 607 else it is an unsigned 16. */ 608 struct { 609 Bool syned; 610 Bool sz32; /* mode64 has both 32 and 64bit cmp */ 611 UInt crfD; 612 HReg srcL; 613 PPCRH* srcR; 614 } Cmp; 615 /* Not, Neg, Clz32/64, Extsw */ 616 struct { 617 PPCUnaryOp op; 618 HReg dst; 619 HReg src; 620 } Unary; 621 struct { 622 Bool syned; /* meaningless if hi32==False */ 623 Bool hi; /* False=>low, True=>high */ 624 Bool sz32; /* mode64 has both 32 & 64bit mull */ 625 HReg dst; 626 HReg srcL; 627 HReg srcR; 628 } MulL; 629 /* ppc32 div/divu instruction. */ 630 struct { 631 Bool extended; 632 Bool syned; 633 Bool sz32; /* mode64 has both 32 & 64bit div */ 634 HReg dst; 635 HReg srcL; 636 HReg srcR; 637 } Div; 638 /* Pseudo-insn. Call target (an absolute address), on given 639 condition (which could be Pct_ALWAYS). argiregs indicates 640 which of r3 .. r10 carries argument values for this call, 641 using a bit mask (1<<N is set if rN holds an arg, for N in 642 3 .. 10 inclusive). */ 643 struct { 644 PPCCondCode cond; 645 Addr64 target; 646 UInt argiregs; 647 RetLoc rloc; /* where the return value will be */ 648 } Call; 649 /* Update the guest CIA value, then exit requesting to chain 650 to it. May be conditional. Use of Addr64 in order to cope 651 with 64-bit hosts. */ 652 struct { 653 Addr64 dstGA; /* next guest address */ 654 PPCAMode* amCIA; /* amode in guest state for CIA */ 655 PPCCondCode cond; /* can be ALWAYS */ 656 Bool toFastEP; /* chain to the slow or fast point? */ 657 } XDirect; 658 /* Boring transfer to a guest address not known at JIT time. 659 Not chainable. May be conditional. */ 660 struct { 661 HReg dstGA; 662 PPCAMode* amCIA; 663 PPCCondCode cond; /* can be ALWAYS */ 664 } XIndir; 665 /* Assisted transfer to a guest address, most general case. 666 Not chainable. May be conditional. */ 667 struct { 668 HReg dstGA; 669 PPCAMode* amCIA; 670 PPCCondCode cond; /* can be ALWAYS */ 671 IRJumpKind jk; 672 } XAssisted; 673 /* Mov src to dst on the given condition, which may not 674 be the bogus Pct_ALWAYS. */ 675 struct { 676 PPCCondCode cond; 677 HReg dst; 678 PPCRI* src; 679 } CMov; 680 /* Zero extending loads. Dst size is host word size */ 681 struct { 682 UChar sz; /* 1|2|4|8 */ 683 HReg dst; 684 PPCAMode* src; 685 } Load; 686 /* Load-and-reserve (lwarx, ldarx) */ 687 struct { 688 UChar sz; /* 4|8 */ 689 HReg dst; 690 HReg src; 691 } LoadL; 692 /* 64/32/16/8 bit stores */ 693 struct { 694 UChar sz; /* 1|2|4|8 */ 695 PPCAMode* dst; 696 HReg src; 697 } Store; 698 /* Store-conditional (stwcx., stdcx.) */ 699 struct { 700 UChar sz; /* 4|8 */ 701 HReg dst; 702 HReg src; 703 } StoreC; 704 /* Convert a ppc condition code to value 0 or 1. */ 705 struct { 706 PPCCondCode cond; 707 HReg dst; 708 } Set; 709 /* Move the entire CR to a GPR */ 710 struct { 711 HReg dst; 712 } MfCR; 713 /* Mem fence. In short, an insn which flushes all preceding 714 loads and stores as much as possible before continuing. 715 On PPC we emit a "sync". */ 716 struct { 717 } MFence; 718 719 /* PPC Floating point */ 720 struct { 721 PPCFpOp op; 722 HReg dst; 723 HReg src; 724 } FpUnary; 725 struct { 726 PPCFpOp op; 727 HReg dst; 728 HReg srcL; 729 HReg srcR; 730 } FpBinary; 731 struct { 732 PPCFpOp op; 733 HReg dst; 734 HReg srcML; 735 HReg srcMR; 736 HReg srcAcc; 737 } FpMulAcc; 738 struct { 739 Bool isLoad; 740 UChar sz; /* only 4 (IEEE single) or 8 (IEEE double) */ 741 HReg reg; 742 PPCAMode* addr; 743 } FpLdSt; 744 struct { 745 HReg addr; /* int reg */ 746 HReg data; /* float reg */ 747 } FpSTFIW; 748 /* Round 64-bit FP value to 32-bit FP value in an FP reg. */ 749 struct { 750 HReg src; 751 HReg dst; 752 } FpRSP; 753 /* fcfid[u,s,us]/fctid[u]/fctiw[u]. Only some combinations 754 of the various fields are allowed. This is asserted for 755 and documented in the code for the constructor, 756 PPCInstr_FpCftI, in host_ppc_defs.c. */ 757 struct { 758 Bool fromI; /* True== I->F, False== F->I */ 759 Bool int32; /* True== I is 32, False== I is 64 */ 760 Bool syned; 761 Bool flt64; /* True== F is 64, False== F is 32 */ 762 HReg src; 763 HReg dst; 764 } FpCftI; 765 /* FP mov src to dst on the given condition. */ 766 struct { 767 PPCCondCode cond; 768 HReg dst; 769 HReg src; 770 } FpCMov; 771 /* Load FP Status & Control Register */ 772 struct { 773 HReg src; 774 UInt dfp_rm; 775 } FpLdFPSCR; 776 /* Do a compare, generating result into an int register. */ 777 struct { 778 UChar crfD; 779 HReg dst; 780 HReg srcL; 781 HReg srcR; 782 } FpCmp; 783 784 /* Read/Write Link Register */ 785 struct { 786 Bool wrLR; 787 HReg gpr; 788 } RdWrLR; 789 790 /* Simplistic AltiVec */ 791 struct { 792 Bool isLoad; 793 UChar sz; /* 8|16|32|128 */ 794 HReg reg; 795 PPCAMode* addr; 796 } AvLdSt; 797 struct { 798 PPCAvOp op; 799 HReg dst; 800 HReg src; 801 } AvUnary; 802 struct { 803 PPCAvOp op; 804 HReg dst; 805 HReg srcL; 806 HReg srcR; 807 } AvBinary; 808 struct { 809 PPCAvOp op; 810 HReg dst; 811 HReg srcL; 812 HReg srcR; 813 } AvBin8x16; 814 struct { 815 PPCAvOp op; 816 HReg dst; 817 HReg srcL; 818 HReg srcR; 819 } AvBin16x8; 820 struct { 821 PPCAvOp op; 822 HReg dst; 823 HReg srcL; 824 HReg srcR; 825 } AvBin32x4; 826 /* Can only be generated for CPUs capable of ISA 2.07 or above */ 827 struct { 828 PPCAvOp op; 829 HReg dst; 830 HReg srcL; 831 HReg srcR; 832 } AvBin64x2; 833 struct { 834 PPCAvFpOp op; 835 HReg dst; 836 HReg srcL; 837 HReg srcR; 838 } AvBin32Fx4; 839 struct { 840 PPCAvFpOp op; 841 HReg dst; 842 HReg src; 843 } AvUn32Fx4; 844 /* Perm,Sel,SlDbl,Splat are all weird AV permutations */ 845 struct { 846 HReg dst; 847 HReg srcL; 848 HReg srcR; 849 HReg ctl; 850 } AvPerm; 851 struct { 852 HReg dst; 853 HReg srcL; 854 HReg srcR; 855 HReg ctl; 856 } AvSel; 857 struct { 858 UChar shift; 859 HReg dst; 860 HReg srcL; 861 HReg srcR; 862 } AvShlDbl; 863 struct { 864 UChar sz; /* 8,16,32 */ 865 HReg dst; 866 PPCVI5s* src; 867 } AvSplat; 868 /* Mov src to dst on the given condition, which may not 869 be the bogus Xcc_ALWAYS. */ 870 struct { 871 PPCCondCode cond; 872 HReg dst; 873 HReg src; 874 } AvCMov; 875 /* Load AltiVec Status & Control Register */ 876 struct { 877 HReg src; 878 } AvLdVSCR; 879 struct { 880 PPCAvOp op; 881 HReg dst; 882 HReg src; 883 } AvCipherV128Unary; 884 struct { 885 PPCAvOp op; 886 HReg dst; 887 HReg src; 888 PPCRI* s_field; 889 } AvHashV128Binary; 890 struct { 891 PPCAvOp op; 892 HReg dst; 893 HReg src1; 894 HReg src2; 895 PPCRI* ps; 896 } AvBCDV128Trinary; 897 struct { 898 PPCAvOp op; 899 HReg dst; 900 HReg srcL; 901 HReg srcR; 902 } AvCipherV128Binary; 903 struct { 904 PPCFpOp op; 905 HReg dst; 906 HReg src; 907 } Dfp64Unary; 908 struct { 909 PPCFpOp op; 910 HReg dst; 911 HReg srcL; 912 HReg srcR; 913 } Dfp64Binary; 914 struct { 915 PPCFpOp op; 916 HReg dst; 917 HReg src; 918 PPCRI* shift; 919 } DfpShift; 920 struct { 921 PPCFpOp op; 922 HReg dst_hi; 923 HReg dst_lo; 924 HReg src_hi; 925 HReg src_lo; 926 } Dfp128Unary; 927 struct { 928 /* The dst is used to pass the left source operand in and return 929 * the result. 930 */ 931 PPCFpOp op; 932 HReg dst_hi; 933 HReg dst_lo; 934 HReg srcR_hi; 935 HReg srcR_lo; 936 } Dfp128Binary; 937 struct { 938 PPCFpOp op; 939 HReg dst_hi; 940 HReg dst_lo; 941 HReg src_hi; 942 HReg src_lo; 943 PPCRI* shift; 944 } DfpShift128; 945 struct { 946 HReg dst; 947 HReg src; 948 PPCRI* r_rmc; 949 } DfpRound; 950 struct { 951 HReg dst_hi; 952 HReg dst_lo; 953 HReg src_hi; 954 HReg src_lo; 955 PPCRI* r_rmc; 956 } DfpRound128; 957 struct { 958 PPCFpOp op; 959 HReg dst; 960 HReg srcL; 961 HReg srcR; 962 PPCRI* rmc; 963 } DfpQuantize; 964 struct { 965 PPCFpOp op; 966 HReg dst_hi; 967 HReg dst_lo; 968 HReg src_hi; 969 HReg src_lo; 970 PPCRI* rmc; 971 } DfpQuantize128; 972 struct { 973 PPCFpOp op; 974 HReg dst; 975 HReg src_hi; 976 HReg src_lo; 977 } ExtractExpD128; 978 struct { 979 PPCFpOp op; 980 HReg dst_hi; 981 HReg dst_lo; 982 HReg srcL; 983 HReg srcR_hi; 984 HReg srcR_lo; 985 } InsertExpD128; 986 struct { 987 PPCFpOp op; 988 HReg dst; 989 HReg src_hi; 990 HReg src_lo; 991 } DfpD128toD64; 992 struct { 993 PPCFpOp op; 994 HReg dst_hi; 995 HReg dst_lo; 996 HReg src; 997 } DfpI64StoD128; 998 struct { 999 UChar crfD; 1000 HReg dst; 1001 HReg srcL; 1002 HReg srcR; 1003 } Dfp64Cmp; 1004 struct { 1005 UChar crfD; 1006 HReg dst; 1007 HReg srcL_hi; 1008 HReg srcL_lo; 1009 HReg srcR_hi; 1010 HReg srcR_lo; 1011 } Dfp128Cmp; 1012 struct { 1013 PPCAMode* amCounter; 1014 PPCAMode* amFailAddr; 1015 } EvCheck; 1016 struct { 1017 /* No fields. The address of the counter to inc is 1018 installed later, post-translation, by patching it in, 1019 as it is not known at translation time. */ 1020 } ProfInc; 1021 } Pin; 1022 } 1023 PPCInstr; 1024 1025 1026 extern PPCInstr* PPCInstr_LI ( HReg, ULong, Bool ); 1027 extern PPCInstr* PPCInstr_Alu ( PPCAluOp, HReg, HReg, PPCRH* ); 1028 extern PPCInstr* PPCInstr_Shft ( PPCShftOp, Bool sz32, HReg, HReg, PPCRH* ); 1029 extern PPCInstr* PPCInstr_AddSubC ( Bool, Bool, HReg, HReg, HReg ); 1030 extern PPCInstr* PPCInstr_Cmp ( Bool, Bool, UInt, HReg, PPCRH* ); 1031 extern PPCInstr* PPCInstr_Unary ( PPCUnaryOp op, HReg dst, HReg src ); 1032 extern PPCInstr* PPCInstr_MulL ( Bool syned, Bool hi32, Bool sz32, HReg, HReg, HReg ); 1033 extern PPCInstr* PPCInstr_Div ( Bool extended, Bool syned, Bool sz32, HReg dst, HReg srcL, HReg srcR ); 1034 extern PPCInstr* PPCInstr_Call ( PPCCondCode, Addr64, UInt, RetLoc ); 1035 extern PPCInstr* PPCInstr_XDirect ( Addr64 dstGA, PPCAMode* amCIA, 1036 PPCCondCode cond, Bool toFastEP ); 1037 extern PPCInstr* PPCInstr_XIndir ( HReg dstGA, PPCAMode* amCIA, 1038 PPCCondCode cond ); 1039 extern PPCInstr* PPCInstr_XAssisted ( HReg dstGA, PPCAMode* amCIA, 1040 PPCCondCode cond, IRJumpKind jk ); 1041 extern PPCInstr* PPCInstr_CMov ( PPCCondCode, HReg dst, PPCRI* src ); 1042 extern PPCInstr* PPCInstr_Load ( UChar sz, 1043 HReg dst, PPCAMode* src, Bool mode64 ); 1044 extern PPCInstr* PPCInstr_LoadL ( UChar sz, 1045 HReg dst, HReg src, Bool mode64 ); 1046 extern PPCInstr* PPCInstr_Store ( UChar sz, PPCAMode* dst, 1047 HReg src, Bool mode64 ); 1048 extern PPCInstr* PPCInstr_StoreC ( UChar sz, HReg dst, HReg src, 1049 Bool mode64 ); 1050 extern PPCInstr* PPCInstr_Set ( PPCCondCode cond, HReg dst ); 1051 extern PPCInstr* PPCInstr_MfCR ( HReg dst ); 1052 extern PPCInstr* PPCInstr_MFence ( void ); 1053 1054 extern PPCInstr* PPCInstr_FpUnary ( PPCFpOp op, HReg dst, HReg src ); 1055 extern PPCInstr* PPCInstr_FpBinary ( PPCFpOp op, HReg dst, HReg srcL, HReg srcR ); 1056 extern PPCInstr* PPCInstr_FpMulAcc ( PPCFpOp op, HReg dst, HReg srcML, 1057 HReg srcMR, HReg srcAcc ); 1058 extern PPCInstr* PPCInstr_FpLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); 1059 extern PPCInstr* PPCInstr_FpSTFIW ( HReg addr, HReg data ); 1060 extern PPCInstr* PPCInstr_FpRSP ( HReg dst, HReg src ); 1061 extern PPCInstr* PPCInstr_FpCftI ( Bool fromI, Bool int32, Bool syned, 1062 Bool dst64, HReg dst, HReg src ); 1063 extern PPCInstr* PPCInstr_FpCMov ( PPCCondCode, HReg dst, HReg src ); 1064 extern PPCInstr* PPCInstr_FpLdFPSCR ( HReg src, Bool dfp_rm ); 1065 extern PPCInstr* PPCInstr_FpCmp ( HReg dst, HReg srcL, HReg srcR ); 1066 1067 extern PPCInstr* PPCInstr_RdWrLR ( Bool wrLR, HReg gpr ); 1068 1069 extern PPCInstr* PPCInstr_AvLdSt ( Bool isLoad, UChar sz, HReg, PPCAMode* ); 1070 extern PPCInstr* PPCInstr_AvUnary ( PPCAvOp op, HReg dst, HReg src ); 1071 extern PPCInstr* PPCInstr_AvBinary ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 1072 extern PPCInstr* PPCInstr_AvBin8x16 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 1073 extern PPCInstr* PPCInstr_AvBin16x8 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 1074 extern PPCInstr* PPCInstr_AvBin32x4 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 1075 extern PPCInstr* PPCInstr_AvBin64x2 ( PPCAvOp op, HReg dst, HReg srcL, HReg srcR ); 1076 extern PPCInstr* PPCInstr_AvBin32Fx4 ( PPCAvFpOp op, HReg dst, HReg srcL, HReg srcR ); 1077 extern PPCInstr* PPCInstr_AvUn32Fx4 ( PPCAvFpOp op, HReg dst, HReg src ); 1078 extern PPCInstr* PPCInstr_AvPerm ( HReg dst, HReg srcL, HReg srcR, HReg ctl ); 1079 extern PPCInstr* PPCInstr_AvSel ( HReg ctl, HReg dst, HReg srcL, HReg srcR ); 1080 extern PPCInstr* PPCInstr_AvShlDbl ( UChar shift, HReg dst, HReg srcL, HReg srcR ); 1081 extern PPCInstr* PPCInstr_AvSplat ( UChar sz, HReg dst, PPCVI5s* src ); 1082 extern PPCInstr* PPCInstr_AvCMov ( PPCCondCode, HReg dst, HReg src ); 1083 extern PPCInstr* PPCInstr_AvLdVSCR ( HReg src ); 1084 extern PPCInstr* PPCInstr_AvCipherV128Unary ( PPCAvOp op, HReg dst, 1085 HReg srcR ); 1086 extern PPCInstr* PPCInstr_AvCipherV128Binary ( PPCAvOp op, HReg dst, 1087 HReg srcL, HReg srcR ); 1088 extern PPCInstr* PPCInstr_AvHashV128Binary ( PPCAvOp op, HReg dst, 1089 HReg src, PPCRI* s_field ); 1090 extern PPCInstr* PPCInstr_AvBCDV128Trinary ( PPCAvOp op, HReg dst, 1091 HReg src1, HReg src2, 1092 PPCRI* ps ); 1093 extern PPCInstr* PPCInstr_Dfp64Unary ( PPCFpOp op, HReg dst, HReg src ); 1094 extern PPCInstr* PPCInstr_Dfp64Binary ( PPCFpOp op, HReg dst, HReg srcL, 1095 HReg srcR ); 1096 extern PPCInstr* PPCInstr_DfpShift ( PPCFpOp op, HReg dst, HReg src, 1097 PPCRI* shift ); 1098 extern PPCInstr* PPCInstr_Dfp128Unary ( PPCFpOp op, HReg dst_hi, HReg dst_lo, 1099 HReg srcR_hi, HReg srcR_lo ); 1100 extern PPCInstr* PPCInstr_Dfp128Binary ( PPCFpOp op, HReg dst_hi, HReg dst_lo, 1101 HReg srcR_hi, HReg srcR_lo ); 1102 extern PPCInstr* PPCInstr_DfpShift128 ( PPCFpOp op, HReg dst_hi, HReg src_hi, 1103 HReg dst_lo, HReg src_lo, 1104 PPCRI* shift ); 1105 extern PPCInstr* PPCInstr_DfpD128toD64 ( PPCFpOp op, HReg dst, 1106 HReg dst_lo, HReg src_lo); 1107 extern PPCInstr* PPCInstr_DfpI64StoD128 ( PPCFpOp op, HReg dst_hi, 1108 HReg dst_lo, HReg src); 1109 extern PPCInstr* PPCInstr_DfpRound ( HReg dst, HReg src, PPCRI* r_rmc ); 1110 extern PPCInstr* PPCInstr_DfpRound128 ( HReg dst_hi, HReg dst_lo, HReg src_hi, 1111 HReg src_lo, PPCRI* r_rmc ); 1112 extern PPCInstr* PPCInstr_DfpQuantize ( PPCFpOp op, HReg dst, HReg srcL, 1113 HReg srcR, PPCRI* rmc ); 1114 extern PPCInstr* PPCInstr_DfpQuantize128 ( PPCFpOp op, HReg dst_hi, 1115 HReg dst_lo, 1116 HReg src_hi, 1117 HReg src_lo, PPCRI* rmc ); 1118 extern PPCInstr* PPCInstr_ExtractExpD128 ( PPCFpOp op, HReg dst, 1119 HReg src_hi, HReg src_lo ); 1120 extern PPCInstr* PPCInstr_InsertExpD128 ( PPCFpOp op, HReg dst_hi, 1121 HReg dst_lo, HReg srcL, 1122 HReg srcR_hi, HReg srcR_lo ); 1123 extern PPCInstr* PPCInstr_Dfp64Cmp ( HReg dst, HReg srcL, HReg srcR ); 1124 extern PPCInstr* PPCInstr_Dfp128Cmp ( HReg dst, HReg srcL_hi, HReg srcL_lo, 1125 HReg srcR_hi, HReg srcR_lo ); 1126 extern PPCInstr* PPCInstr_EvCheck ( PPCAMode* amCounter, 1127 PPCAMode* amFailAddr ); 1128 extern PPCInstr* PPCInstr_ProfInc ( void ); 1129 1130 extern void ppPPCInstr(PPCInstr*, Bool mode64); 1131 1132 1133 /* Some functions that insulate the register allocator from details 1134 of the underlying instruction set. */ 1135 extern void getRegUsage_PPCInstr ( HRegUsage*, PPCInstr*, Bool mode64 ); 1136 extern void mapRegs_PPCInstr ( HRegRemap*, PPCInstr* , Bool mode64); 1137 extern Bool isMove_PPCInstr ( PPCInstr*, HReg*, HReg* ); 1138 extern Int emit_PPCInstr ( /*MB_MOD*/Bool* is_profInc, 1139 UChar* buf, Int nbuf, PPCInstr* i, 1140 Bool mode64, 1141 void* disp_cp_chain_me_to_slowEP, 1142 void* disp_cp_chain_me_to_fastEP, 1143 void* disp_cp_xindir, 1144 void* disp_cp_xassisted ); 1145 1146 extern void genSpill_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 1147 HReg rreg, Int offsetB, Bool mode64 ); 1148 extern void genReload_PPC ( /*OUT*/HInstr** i1, /*OUT*/HInstr** i2, 1149 HReg rreg, Int offsetB, Bool mode64 ); 1150 1151 extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 ); 1152 extern HInstrArray* iselSB_PPC ( IRSB*, 1153 VexArch, 1154 VexArchInfo*, 1155 VexAbiInfo*, 1156 Int offs_Host_EvC_Counter, 1157 Int offs_Host_EvC_FailAddr, 1158 Bool chainingAllowed, 1159 Bool addProfInc, 1160 Addr64 max_ga ); 1161 1162 /* How big is an event check? This is kind of a kludge because it 1163 depends on the offsets of host_EvC_FAILADDR and 1164 host_EvC_COUNTER. */ 1165 extern Int evCheckSzB_PPC ( void ); 1166 1167 /* Perform a chaining and unchaining of an XDirect jump. */ 1168 extern VexInvalRange chainXDirect_PPC ( void* place_to_chain, 1169 void* disp_cp_chain_me_EXPECTED, 1170 void* place_to_jump_to, 1171 Bool mode64 ); 1172 1173 extern VexInvalRange unchainXDirect_PPC ( void* place_to_unchain, 1174 void* place_to_jump_to_EXPECTED, 1175 void* disp_cp_chain_me, 1176 Bool mode64 ); 1177 1178 /* Patch the counter location into an existing ProfInc point. */ 1179 extern VexInvalRange patchProfInc_PPC ( void* place_to_patch, 1180 ULong* location_of_counter, 1181 Bool mode64 ); 1182 1183 1184 #endif /* ndef __VEX_HOST_PPC_DEFS_H */ 1185 1186 /*---------------------------------------------------------------*/ 1187 /*--- end host_ppc_defs.h ---*/ 1188 /*---------------------------------------------------------------*/ 1189
