1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" 2 target triple = "armv7-none-linux-gnueabi" 3 4 declare i8* @rsOffset([1 x i32] %a.coerce, i32 %sizeOf, i32 %x, i32 %y, i32 %z) 5 declare i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) 6 7 ; The loads and stores in this file are annotated with RenderScript-specific 8 ; information for the type based alias analysis, such that the TBAA analysis 9 ; understands that loads and stores from two allocations with different types 10 ; can never access the same memory element. This is different from C, where 11 ; a char or uchar load/store is special as it can alias with about everything. 12 ; 13 ; The TBAA tree in this file has the the node "RenderScript TBAA" as its root. 14 ; This means all loads/stores that share this common root can be proven to not 15 ; alias. However, the alias analysis still has to assume MayAlias between 16 ; memory accesses in this file and memory accesses annotated with the C/C++ 17 ; TBAA metadata. 18 ; If we can ensure that all accesses to elements loaded from RenderScript 19 ; allocations are either annotated with the RenderScript TBAA information or 20 ; not annotated at all, but never annotated with the C/C++ metadata, we 21 ; can add the RenderScript TBAA tree under the C/C++ TBAA tree. This enables 22 ; then the TBAA to prove that an access to data from the RenderScript allocation 23 ; does not alias with a load/store accessing something not part of a RenderScript 24 ; allocation. 25 26 27 !14 = metadata !{metadata !"RenderScript TBAA"} 28 !15 = metadata !{metadata !"allocation", metadata !14} 29 30 !21 = metadata !{metadata !"char", metadata !15} 31 define void @rsSetElementAtImpl_char([1 x i32] %a.coerce, i8 signext %val, i32 %x, i32 %y, i32 %z) #1 { 32 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 33 store i8 %val, i8* %1, align 1, !tbaa !21 34 ret void 35 } 36 37 define signext i8 @rsGetElementAtImpl_char([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 38 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 39 %2 = load i8* %1, align 1, !tbaa !21 40 ret i8 %2 41 } 42 43 !22 = metadata !{metadata !"char2", metadata !15} 44 define void @rsSetElementAtImpl_char2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 45 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 46 %2 = bitcast i8* %1 to <2 x i8>* 47 store <2 x i8> %val, <2 x i8>* %2, align 2, !tbaa !22 48 ret void 49 } 50 51 define <2 x i8> @rsGetElementAtImpl_char2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 52 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 53 %2 = bitcast i8* %1 to <2 x i8>* 54 %3 = load <2 x i8>* %2, align 2, !tbaa !22 55 ret <2 x i8> %3 56 } 57 58 !23 = metadata !{metadata !"char3", metadata !15} 59 define void @rsSetElementAtImpl_char3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 60 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 61 %2 = shufflevector <3 x i8> %val, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 62 %3 = bitcast i8* %1 to <4 x i8>* 63 store <4 x i8> %2, <4 x i8>* %3, align 4, !tbaa !23 64 ret void 65 } 66 67 define <3 x i8> @rsGetElementAtImpl_char3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 68 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 69 %2 = bitcast i8* %1 to <4 x i8>* 70 %3 = load <4 x i8>* %2, align 4, !tbaa !23 71 %4 = shufflevector <4 x i8> %3, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> 72 ret <3 x i8> %4 73 } 74 75 !24 = metadata !{metadata !"char4", metadata !15} 76 define void @rsSetElementAtImpl_char4([1 x i32] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 77 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 78 %2 = bitcast i8* %1 to <4 x i8>* 79 store <4 x i8> %val, <4 x i8>* %2, align 4, !tbaa !24 80 ret void 81 } 82 83 define <4 x i8> @rsGetElementAtImpl_char4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 84 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 85 %2 = bitcast i8* %1 to <4 x i8>* 86 %3 = load <4 x i8>* %2, align 4, !tbaa !24 87 ret <4 x i8> %3 88 } 89 90 !25 = metadata !{metadata !"uchar", metadata !15} 91 define void @rsSetElementAtImpl_uchar([1 x i32] %a.coerce, i8 zeroext %val, i32 %x, i32 %y, i32 %z) #1 { 92 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 93 store i8 %val, i8* %1, align 1, !tbaa !25 94 ret void 95 } 96 97 define zeroext i8 @rsGetElementAtImpl_uchar([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 98 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 99 %2 = load i8* %1, align 1, !tbaa !25 100 ret i8 %2 101 } 102 103 !26 = metadata !{metadata !"uchar2", metadata !15} 104 define void @rsSetElementAtImpl_uchar2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 105 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 106 %2 = bitcast i8* %1 to <2 x i8>* 107 store <2 x i8> %val, <2 x i8>* %2, align 2, !tbaa !26 108 ret void 109 } 110 111 define <2 x i8> @rsGetElementAtImpl_uchar2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 112 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 113 %2 = bitcast i8* %1 to <2 x i8>* 114 %3 = load <2 x i8>* %2, align 2, !tbaa !26 115 ret <2 x i8> %3 116 } 117 118 !27 = metadata !{metadata !"uchar3", metadata !15} 119 define void @rsSetElementAtImpl_uchar3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 120 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 121 %2 = shufflevector <3 x i8> %val, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 122 %3 = bitcast i8* %1 to <4 x i8>* 123 store <4 x i8> %2, <4 x i8>* %3, align 4, !tbaa !27 124 ret void 125 } 126 127 define <3 x i8> @rsGetElementAtImpl_uchar3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 128 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 129 %2 = bitcast i8* %1 to <4 x i8>* 130 %3 = load <4 x i8>* %2, align 4, !tbaa !27 131 %4 = shufflevector <4 x i8> %3, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> 132 ret <3 x i8> %4 133 } 134 135 !28 = metadata !{metadata !"uchar4", metadata !15} 136 define void @rsSetElementAtImpl_uchar4([1 x i32] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 137 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 138 %2 = bitcast i8* %1 to <4 x i8>* 139 store <4 x i8> %val, <4 x i8>* %2, align 4, !tbaa !28 140 ret void 141 } 142 143 define <4 x i8> @rsGetElementAtImpl_uchar4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 144 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 145 %2 = bitcast i8* %1 to <4 x i8>* 146 %3 = load <4 x i8>* %2, align 4, !tbaa !28 147 ret <4 x i8> %3 148 } 149 150 !29 = metadata !{metadata !"short", metadata !15} 151 define void @rsSetElementAtImpl_short([1 x i32] %a.coerce, i16 signext %val, i32 %x, i32 %y, i32 %z) #1 { 152 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 153 %2 = bitcast i8* %1 to i16* 154 store i16 %val, i16* %2, align 2, !tbaa !29 155 ret void 156 } 157 158 define signext i16 @rsGetElementAtImpl_short([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 159 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 160 %2 = bitcast i8* %1 to i16* 161 %3 = load i16* %2, align 2, !tbaa !29 162 ret i16 %3 163 } 164 165 !30 = metadata !{metadata !"short2", metadata !15} 166 define void @rsSetElementAtImpl_short2([1 x i32] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 167 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 168 %2 = bitcast i8* %1 to <2 x i16>* 169 store <2 x i16> %val, <2 x i16>* %2, align 4, !tbaa !30 170 ret void 171 } 172 173 define <2 x i16> @rsGetElementAtImpl_short2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 174 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 175 %2 = bitcast i8* %1 to <2 x i16>* 176 %3 = load <2 x i16>* %2, align 4, !tbaa !30 177 ret <2 x i16> %3 178 } 179 180 !31 = metadata !{metadata !"short3", metadata !15} 181 define void @rsSetElementAtImpl_short3([1 x i32] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 182 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 183 %2 = shufflevector <3 x i16> %val, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 184 %3 = bitcast i8* %1 to <4 x i16>* 185 store <4 x i16> %2, <4 x i16>* %3, align 8, !tbaa !31 186 ret void 187 } 188 189 define <3 x i16> @rsGetElementAtImpl_short3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 190 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 191 %2 = bitcast i8* %1 to <4 x i16>* 192 %3 = load <4 x i16>* %2, align 8, !tbaa !31 193 %4 = shufflevector <4 x i16> %3, <4 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2> 194 ret <3 x i16> %4 195 } 196 197 !32 = metadata !{metadata !"short4", metadata !15} 198 define void @rsSetElementAtImpl_short4([1 x i32] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 199 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 200 %2 = bitcast i8* %1 to <4 x i16>* 201 store <4 x i16> %val, <4 x i16>* %2, align 8, !tbaa !32 202 ret void 203 } 204 205 define <4 x i16> @rsGetElementAtImpl_short4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 206 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 207 %2 = bitcast i8* %1 to <4 x i16>* 208 %3 = load <4 x i16>* %2, align 8, !tbaa !32 209 ret <4 x i16> %3 210 } 211 212 !33 = metadata !{metadata !"ushort", metadata !15} 213 define void @rsSetElementAtImpl_ushort([1 x i32] %a.coerce, i16 zeroext %val, i32 %x, i32 %y, i32 %z) #1 { 214 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 215 %2 = bitcast i8* %1 to i16* 216 store i16 %val, i16* %2, align 2, !tbaa !33 217 ret void 218 } 219 220 define zeroext i16 @rsGetElementAtImpl_ushort([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 221 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 222 %2 = bitcast i8* %1 to i16* 223 %3 = load i16* %2, align 2, !tbaa !33 224 ret i16 %3 225 } 226 227 !34 = metadata !{metadata !"ushort2", metadata !15} 228 define void @rsSetElementAtImpl_ushort2([1 x i32] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 229 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 230 %2 = bitcast i8* %1 to <2 x i16>* 231 store <2 x i16> %val, <2 x i16>* %2, align 4, !tbaa !34 232 ret void 233 } 234 235 define <2 x i16> @rsGetElementAtImpl_ushort2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 236 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 237 %2 = bitcast i8* %1 to <2 x i16>* 238 %3 = load <2 x i16>* %2, align 4, !tbaa !34 239 ret <2 x i16> %3 240 } 241 242 !35 = metadata !{metadata !"ushort3", metadata !15} 243 define void @rsSetElementAtImpl_ushort3([1 x i32] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 244 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 245 %2 = shufflevector <3 x i16> %val, <3 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 246 %3 = bitcast i8* %1 to <4 x i16>* 247 store <4 x i16> %2, <4 x i16>* %3, align 8, !tbaa !35 248 ret void 249 } 250 251 define <3 x i16> @rsGetElementAtImpl_ushort3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 252 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 253 %2 = bitcast i8* %1 to <4 x i16>* 254 %3 = load <4 x i16>* %2, align 8, !tbaa !35 255 %4 = shufflevector <4 x i16> %3, <4 x i16> undef, <3 x i32> <i32 0, i32 1, i32 2> 256 ret <3 x i16> %4 257 } 258 259 !36 = metadata !{metadata !"ushort4", metadata !15} 260 define void @rsSetElementAtImpl_ushort4([1 x i32] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 261 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 262 %2 = bitcast i8* %1 to <4 x i16>* 263 store <4 x i16> %val, <4 x i16>* %2, align 8, !tbaa !36 264 ret void 265 } 266 267 define <4 x i16> @rsGetElementAtImpl_ushort4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 268 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 269 %2 = bitcast i8* %1 to <4 x i16>* 270 %3 = load <4 x i16>* %2, align 8, !tbaa !36 271 ret <4 x i16> %3 272 } 273 274 !37 = metadata !{metadata !"int", metadata !15} 275 define void @rsSetElementAtImpl_int([1 x i32] %a.coerce, i32 %val, i32 %x, i32 %y, i32 %z) #1 { 276 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 277 %2 = bitcast i8* %1 to i32* 278 store i32 %val, i32* %2, align 4, !tbaa !37 279 ret void 280 } 281 282 define i32 @rsGetElementAtImpl_int([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 283 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 284 %2 = bitcast i8* %1 to i32* 285 %3 = load i32* %2, align 4, !tbaa !37 286 ret i32 %3 287 } 288 289 !38 = metadata !{metadata !"int2", metadata !15} 290 define void @rsSetElementAtImpl_int2([1 x i32] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 291 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 292 %2 = bitcast i8* %1 to <2 x i32>* 293 store <2 x i32> %val, <2 x i32>* %2, align 8, !tbaa !38 294 ret void 295 } 296 297 define <2 x i32> @rsGetElementAtImpl_int2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 298 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 299 %2 = bitcast i8* %1 to <2 x i32>* 300 %3 = load <2 x i32>* %2, align 8, !tbaa !38 301 ret <2 x i32> %3 302 } 303 304 !39 = metadata !{metadata !"int3", metadata !15} 305 define void @rsSetElementAtImpl_int3([1 x i32] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 306 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 307 %2 = shufflevector <3 x i32> %val, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 308 %3 = bitcast i8* %1 to <4 x i32>* 309 store <4 x i32> %2, <4 x i32>* %3, align 16, !tbaa !39 310 ret void 311 } 312 313 define <3 x i32> @rsGetElementAtImpl_int3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 314 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 315 %2 = bitcast i8* %1 to <4 x i32>* 316 %3 = load <4 x i32>* %2, align 8, !tbaa !39 317 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2> 318 ret <3 x i32> %4 319 } 320 321 !40 = metadata !{metadata !"int4", metadata !15} 322 define void @rsSetElementAtImpl_int4([1 x i32] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 323 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 324 %2 = bitcast i8* %1 to <4 x i32>* 325 store <4 x i32> %val, <4 x i32>* %2, align 16, !tbaa !40 326 ret void 327 } 328 329 define <4 x i32> @rsGetElementAtImpl_int4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 330 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 331 %2 = bitcast i8* %1 to <4 x i32>* 332 %3 = load <4 x i32>* %2, align 16, !tbaa !40 333 ret <4 x i32> %3 334 } 335 336 !41 = metadata !{metadata !"uint", metadata !15} 337 define void @rsSetElementAtImpl_uint([1 x i32] %a.coerce, i32 %val, i32 %x, i32 %y, i32 %z) #1 { 338 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 339 %2 = bitcast i8* %1 to i32* 340 store i32 %val, i32* %2, align 4, !tbaa !41 341 ret void 342 } 343 344 define i32 @rsGetElementAtImpl_uint([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 345 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 346 %2 = bitcast i8* %1 to i32* 347 %3 = load i32* %2, align 4, !tbaa !41 348 ret i32 %3 349 } 350 351 !42 = metadata !{metadata !"uint2", metadata !15} 352 define void @rsSetElementAtImpl_uint2([1 x i32] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 353 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 354 %2 = bitcast i8* %1 to <2 x i32>* 355 store <2 x i32> %val, <2 x i32>* %2, align 8, !tbaa !42 356 ret void 357 } 358 359 define <2 x i32> @rsGetElementAtImpl_uint2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 360 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 361 %2 = bitcast i8* %1 to <2 x i32>* 362 %3 = load <2 x i32>* %2, align 8, !tbaa !42 363 ret <2 x i32> %3 364 } 365 366 !43 = metadata !{metadata !"uint3", metadata !15} 367 define void @rsSetElementAtImpl_uint3([1 x i32] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 368 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 369 %2 = shufflevector <3 x i32> %val, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 370 %3 = bitcast i8* %1 to <4 x i32>* 371 store <4 x i32> %2, <4 x i32>* %3, align 16, !tbaa !43 372 ret void 373 } 374 375 define <3 x i32> @rsGetElementAtImpl_uint3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 376 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 377 %2 = bitcast i8* %1 to <4 x i32>* 378 %3 = load <4 x i32>* %2, align 8, !tbaa !43 379 %4 = shufflevector <4 x i32> %3, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2> 380 ret <3 x i32> %4 381 } 382 383 !44 = metadata !{metadata !"uint4", metadata !15} 384 define void @rsSetElementAtImpl_uint4([1 x i32] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 385 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 386 %2 = bitcast i8* %1 to <4 x i32>* 387 store <4 x i32> %val, <4 x i32>* %2, align 16, !tbaa !44 388 ret void 389 } 390 391 define <4 x i32> @rsGetElementAtImpl_uint4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 392 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 393 %2 = bitcast i8* %1 to <4 x i32>* 394 %3 = load <4 x i32>* %2, align 16, !tbaa !44 395 ret <4 x i32> %3 396 } 397 398 !45 = metadata !{metadata !"long", metadata !15} 399 define void @rsSetElementAtImpl_long([1 x i32] %a.coerce, i64 %val, i32 %x, i32 %y, i32 %z) #1 { 400 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 401 %2 = bitcast i8* %1 to i64* 402 store i64 %val, i64* %2, align 8, !tbaa !45 403 ret void 404 } 405 406 define i64 @rsGetElementAtImpl_long([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 407 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 408 %2 = bitcast i8* %1 to i64* 409 %3 = load i64* %2, align 8, !tbaa !45 410 ret i64 %3 411 } 412 413 !46 = metadata !{metadata !"long2", metadata !15} 414 define void @rsSetElementAtImpl_long2([1 x i32] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 415 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 416 %2 = bitcast i8* %1 to <2 x i64>* 417 store <2 x i64> %val, <2 x i64>* %2, align 16, !tbaa !46 418 ret void 419 } 420 421 define <2 x i64> @rsGetElementAtImpl_long2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 422 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 423 %2 = bitcast i8* %1 to <2 x i64>* 424 %3 = load <2 x i64>* %2, align 16, !tbaa !46 425 ret <2 x i64> %3 426 } 427 428 !47 = metadata !{metadata !"long3", metadata !15} 429 define void @rsSetElementAtImpl_long3([1 x i32] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 430 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 431 %2 = shufflevector <3 x i64> %val, <3 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 432 %3 = bitcast i8* %1 to <4 x i64>* 433 store <4 x i64> %2, <4 x i64>* %3, align 32, !tbaa !47 434 ret void 435 } 436 437 define void @rsGetElementAtImpl_long3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 438 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 439 %2 = bitcast i8* %1 to <4 x i64>* 440 %3 = load <4 x i64>* %2, align 32 441 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 442 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !47 443 ret void 444 } 445 446 !48 = metadata !{metadata !"long4", metadata !15} 447 define void @rsSetElementAtImpl_long4([1 x i32] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 448 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 449 %2 = bitcast i8* %1 to <4 x i64>* 450 store <4 x i64> %val, <4 x i64>* %2, align 32, !tbaa !48 451 ret void 452 } 453 454 define void @rsGetElementAtImpl_long4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 455 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 456 %2 = bitcast i8* %1 to <4 x i64>* 457 %3 = load <4 x i64>* %2, align 32, !tbaa !15 458 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !48 459 ret void 460 } 461 462 !49 = metadata !{metadata !"ulong", metadata !15} 463 define void @rsSetElementAtImpl_ulong([1 x i32] %a.coerce, i64 %val, i32 %x, i32 %y, i32 %z) #1 { 464 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 465 %2 = bitcast i8* %1 to i64* 466 store i64 %val, i64* %2, align 8, !tbaa !49 467 ret void 468 } 469 470 define i64 @rsGetElementAtImpl_ulong([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 471 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 472 %2 = bitcast i8* %1 to i64* 473 %3 = load i64* %2, align 8, !tbaa !49 474 ret i64 %3 475 } 476 477 !50 = metadata !{metadata !"ulong2", metadata !15} 478 define void @rsSetElementAtImpl_ulong2([1 x i32] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 479 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 480 %2 = bitcast i8* %1 to <2 x i64>* 481 store <2 x i64> %val, <2 x i64>* %2, align 16, !tbaa !50 482 ret void 483 } 484 485 define <2 x i64> @rsGetElementAtImpl_ulong2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 486 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 487 %2 = bitcast i8* %1 to <2 x i64>* 488 %3 = load <2 x i64>* %2, align 16, !tbaa !50 489 ret <2 x i64> %3 490 } 491 492 !51 = metadata !{metadata !"ulong3", metadata !15} 493 define void @rsSetElementAtImpl_ulong3([1 x i32] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 494 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 495 %2 = shufflevector <3 x i64> %val, <3 x i64> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 496 %3 = bitcast i8* %1 to <4 x i64>* 497 store <4 x i64> %2, <4 x i64>* %3, align 32, !tbaa !51 498 ret void 499 } 500 501 define void @rsGetElementAtImpl_ulong3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 502 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 503 %2 = bitcast i8* %1 to <4 x i64>* 504 %3 = load <4 x i64>* %2, align 32 505 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 506 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !51 507 ret void 508 } 509 510 !52 = metadata !{metadata !"ulong4", metadata !15} 511 define void @rsSetElementAtImpl_ulong4([1 x i32] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 512 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 513 %2 = bitcast i8* %1 to <4 x i64>* 514 store <4 x i64> %val, <4 x i64>* %2, align 32, !tbaa !52 515 ret void 516 } 517 518 define void @rsGetElementAtImpl_ulong4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 519 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 520 %2 = bitcast i8* %1 to <4 x i64>* 521 %3 = load <4 x i64>* %2, align 32, !tbaa !15 522 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !52 523 ret void 524 } 525 526 !53 = metadata !{metadata !"float", metadata !15} 527 define void @rsSetElementAtImpl_float([1 x i32] %a.coerce, float %val, i32 %x, i32 %y, i32 %z) #1 { 528 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 529 %2 = bitcast i8* %1 to float* 530 store float %val, float* %2, align 4, !tbaa !53 531 ret void 532 } 533 534 define float @rsGetElementAtImpl_float([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 535 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 4, i32 %x, i32 %y, i32 %z) #2 536 %2 = bitcast i8* %1 to float* 537 %3 = load float* %2, align 4, !tbaa !53 538 ret float %3 539 } 540 541 !54 = metadata !{metadata !"float2", metadata !15} 542 define void @rsSetElementAtImpl_float2([1 x i32] %a.coerce, <2 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 543 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 544 %2 = bitcast i8* %1 to <2 x float>* 545 store <2 x float> %val, <2 x float>* %2, align 8, !tbaa !54 546 ret void 547 } 548 549 define <2 x float> @rsGetElementAtImpl_float2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 550 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 551 %2 = bitcast i8* %1 to <2 x float>* 552 %3 = load <2 x float>* %2, align 8, !tbaa !54 553 ret <2 x float> %3 554 } 555 556 !55 = metadata !{metadata !"float3", metadata !15} 557 define void @rsSetElementAtImpl_float3([1 x i32] %a.coerce, <3 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 558 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 559 %2 = shufflevector <3 x float> %val, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 560 %3 = bitcast i8* %1 to <4 x float>* 561 store <4 x float> %2, <4 x float>* %3, align 16, !tbaa !55 562 ret void 563 } 564 565 define <3 x float> @rsGetElementAtImpl_float3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 566 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 567 %2 = bitcast i8* %1 to <4 x float>* 568 %3 = load <4 x float>* %2, align 8, !tbaa !55 569 %4 = shufflevector <4 x float> %3, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 570 ret <3 x float> %4 571 } 572 573 !56 = metadata !{metadata !"float4", metadata !15} 574 define void @rsSetElementAtImpl_float4([1 x i32] %a.coerce, <4 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 575 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 576 %2 = bitcast i8* %1 to <4 x float>* 577 store <4 x float> %val, <4 x float>* %2, align 16, !tbaa !56 578 ret void 579 } 580 581 define <4 x float> @rsGetElementAtImpl_float4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 582 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 583 %2 = bitcast i8* %1 to <4 x float>* 584 %3 = load <4 x float>* %2, align 16, !tbaa !56 585 ret <4 x float> %3 586 } 587 588 !57 = metadata !{metadata !"double", metadata !15} 589 define void @rsSetElementAtImpl_double([1 x i32] %a.coerce, double %val, i32 %x, i32 %y, i32 %z) #1 { 590 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 591 %2 = bitcast i8* %1 to double* 592 store double %val, double* %2, align 8, !tbaa !57 593 ret void 594 } 595 596 define double @rsGetElementAtImpl_double([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 597 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 8, i32 %x, i32 %y, i32 %z) #2 598 %2 = bitcast i8* %1 to double* 599 %3 = load double* %2, align 8, !tbaa !57 600 ret double %3 601 } 602 603 !58 = metadata !{metadata !"double2", metadata !15} 604 define void @rsSetElementAtImpl_double2([1 x i32] %a.coerce, <2 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 605 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 606 %2 = bitcast i8* %1 to <2 x double>* 607 store <2 x double> %val, <2 x double>* %2, align 16, !tbaa !58 608 ret void 609 } 610 611 define <2 x double> @rsGetElementAtImpl_double2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 612 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 16, i32 %x, i32 %y, i32 %z) #2 613 %2 = bitcast i8* %1 to <2 x double>* 614 %3 = load <2 x double>* %2, align 16, !tbaa !58 615 ret <2 x double> %3 616 } 617 618 !59 = metadata !{metadata !"double3", metadata !15} 619 define void @rsSetElementAtImpl_double3([1 x i32] %a.coerce, <3 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 620 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 621 %2 = shufflevector <3 x double> %val, <3 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 622 %3 = bitcast i8* %1 to <4 x double>* 623 store <4 x double> %2, <4 x double>* %3, align 32, !tbaa !59 624 ret void 625 } 626 627 628 define void @rsGetElementAtImpl_double3(<3 x double>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 629 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 630 %2 = bitcast i8* %1 to <4 x double>* 631 %3 = load <4 x double>* %2, align 32 632 %4 = bitcast <3 x double>* %agg.result to <4 x double>* 633 store <4 x double> %3, <4 x double>* %4, align 32, !tbaa !59 634 ret void 635 } 636 637 !60 = metadata !{metadata !"double4", metadata !15} 638 define void @rsSetElementAtImpl_double4([1 x i32] %a.coerce, <4 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 639 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 640 %2 = bitcast i8* %1 to <4 x double>* 641 store <4 x double> %val, <4 x double>* %2, align 32, !tbaa !60 642 ret void 643 } 644 define void @rsGetElementAtImpl_double4(<4 x double>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 645 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 32, i32 %x, i32 %y, i32 %z) #2 646 %2 = bitcast i8* %1 to <4 x double>* 647 %3 = load <4 x double>* %2, align 32, !tbaa !15 648 store <4 x double> %3, <4 x double>* %agg.result, align 32, !tbaa !60 649 ret void 650 } 651 652 653 define void @__rsAllocationVLoadXImpl_long4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 654 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 655 %2 = bitcast i8* %1 to <4 x i64>* 656 %3 = load <4 x i64>* %2, align 8 657 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !52 658 ret void 659 } 660 define void @__rsAllocationVLoadXImpl_long3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 661 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 662 %2 = bitcast i8* %1 to <4 x i64>* 663 %3 = load <4 x i64>* %2, align 8 664 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 665 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !47 666 ret void 667 } 668 define <2 x i64> @__rsAllocationVLoadXImpl_long2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 669 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 670 %2 = bitcast i8* %1 to <2 x i64>* 671 %3 = load <2 x i64>* %2, align 8 672 ret <2 x i64> %3 673 } 674 675 define void @__rsAllocationVLoadXImpl_ulong4(<4 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 676 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 677 %2 = bitcast i8* %1 to <4 x i64>* 678 %3 = load <4 x i64>* %2, align 8 679 store <4 x i64> %3, <4 x i64>* %agg.result, align 32, !tbaa !48 680 ret void 681 } 682 define void @__rsAllocationVLoadXImpl_ulong3(<3 x i64>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 683 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 684 %2 = bitcast i8* %1 to <4 x i64>* 685 %3 = load <4 x i64>* %2, align 8 686 %4 = bitcast <3 x i64>* %agg.result to <4 x i64>* 687 store <4 x i64> %3, <4 x i64>* %4, align 32, !tbaa !51 688 ret void 689 } 690 define <2 x i64> @__rsAllocationVLoadXImpl_ulong2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 691 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 692 %2 = bitcast i8* %1 to <2 x i64>* 693 %3 = load <2 x i64>* %2, align 8 694 ret <2 x i64> %3 695 } 696 697 define <4 x i32> @__rsAllocationVLoadXImpl_int4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 698 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 699 %2 = bitcast i8* %1 to <4 x i32>* 700 %3 = load <4 x i32>* %2, align 4 701 ret <4 x i32> %3 702 } 703 define <3 x i32> @__rsAllocationVLoadXImpl_int3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 704 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 705 %2 = bitcast i8* %1 to <3 x i32>* 706 %3 = load <3 x i32>* %2, align 4 707 ret <3 x i32> %3 708 } 709 define <2 x i32> @__rsAllocationVLoadXImpl_int2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 710 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 711 %2 = bitcast i8* %1 to <2 x i32>* 712 %3 = load <2 x i32>* %2, align 4 713 ret <2 x i32> %3 714 } 715 716 define <4 x i32> @__rsAllocationVLoadXImpl_uint4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 717 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 718 %2 = bitcast i8* %1 to <4 x i32>* 719 %3 = load <4 x i32>* %2, align 4 720 ret <4 x i32> %3 721 } 722 define <3 x i32> @__rsAllocationVLoadXImpl_uint3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 723 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 724 %2 = bitcast i8* %1 to <3 x i32>* 725 %3 = load <3 x i32>* %2, align 4 726 ret <3 x i32> %3 727 } 728 define <2 x i32> @__rsAllocationVLoadXImpl_uint2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 729 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 730 %2 = bitcast i8* %1 to <2 x i32>* 731 %3 = load <2 x i32>* %2, align 4 732 ret <2 x i32> %3 733 } 734 735 define <4 x i16> @__rsAllocationVLoadXImpl_short4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 736 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 737 %2 = bitcast i8* %1 to <4 x i16>* 738 %3 = load <4 x i16>* %2, align 2 739 ret <4 x i16> %3 740 } 741 define <3 x i16> @__rsAllocationVLoadXImpl_short3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 742 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 743 %2 = bitcast i8* %1 to <3 x i16>* 744 %3 = load <3 x i16>* %2, align 2 745 ret <3 x i16> %3 746 } 747 define <2 x i16> @__rsAllocationVLoadXImpl_short2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 748 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 749 %2 = bitcast i8* %1 to <2 x i16>* 750 %3 = load <2 x i16>* %2, align 2 751 ret <2 x i16> %3 752 } 753 754 define <4 x i16> @__rsAllocationVLoadXImpl_ushort4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 755 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 756 %2 = bitcast i8* %1 to <4 x i16>* 757 %3 = load <4 x i16>* %2, align 2 758 ret <4 x i16> %3 759 } 760 define <3 x i16> @__rsAllocationVLoadXImpl_ushort3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 761 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 762 %2 = bitcast i8* %1 to <3 x i16>* 763 %3 = load <3 x i16>* %2, align 2 764 ret <3 x i16> %3 765 } 766 define <2 x i16> @__rsAllocationVLoadXImpl_ushort2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 767 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 768 %2 = bitcast i8* %1 to <2 x i16>* 769 %3 = load <2 x i16>* %2, align 2 770 ret <2 x i16> %3 771 } 772 773 define <4 x i8> @__rsAllocationVLoadXImpl_char4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 774 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 775 %2 = bitcast i8* %1 to <4 x i8>* 776 %3 = load <4 x i8>* %2, align 1 777 ret <4 x i8> %3 778 } 779 define <3 x i8> @__rsAllocationVLoadXImpl_char3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 780 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 781 %2 = bitcast i8* %1 to <3 x i8>* 782 %3 = load <3 x i8>* %2, align 1 783 ret <3 x i8> %3 784 } 785 define <2 x i8> @__rsAllocationVLoadXImpl_char2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 786 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 787 %2 = bitcast i8* %1 to <2 x i8>* 788 %3 = load <2 x i8>* %2, align 1 789 ret <2 x i8> %3 790 } 791 792 define <4 x i8> @__rsAllocationVLoadXImpl_uchar4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 793 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 794 %2 = bitcast i8* %1 to <4 x i8>* 795 %3 = load <4 x i8>* %2, align 1 796 ret <4 x i8> %3 797 } 798 define <3 x i8> @__rsAllocationVLoadXImpl_uchar3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 799 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 800 %2 = bitcast i8* %1 to <3 x i8>* 801 %3 = load <3 x i8>* %2, align 1 802 ret <3 x i8> %3 803 } 804 define <2 x i8> @__rsAllocationVLoadXImpl_uchar2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 805 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 806 %2 = bitcast i8* %1 to <2 x i8>* 807 %3 = load <2 x i8>* %2, align 1 808 ret <2 x i8> %3 809 } 810 811 define <4 x float> @__rsAllocationVLoadXImpl_float4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 812 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 813 %2 = bitcast i8* %1 to <4 x float>* 814 %3 = load <4 x float>* %2, align 4 815 ret <4 x float> %3 816 } 817 define <3 x float> @__rsAllocationVLoadXImpl_float3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 818 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 819 %2 = bitcast i8* %1 to <3 x float>* 820 %3 = load <3 x float>* %2, align 4 821 ret <3 x float> %3 822 } 823 define <2 x float> @__rsAllocationVLoadXImpl_float2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 824 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 825 %2 = bitcast i8* %1 to <2 x float>* 826 %3 = load <2 x float>* %2, align 4 827 ret <2 x float> %3 828 } 829 830 define void @__rsAllocationVLoadXImpl_double4(<4 x double>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 831 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 832 %2 = bitcast i8* %1 to <4 x double>* 833 %3 = load <4 x double>* %2, align 8 834 store <4 x double> %3, <4 x double>* %agg.result, align 32, !tbaa !60 835 ret void 836 } 837 define void @__rsAllocationVLoadXImpl_double3(<3 x double>* noalias nocapture sret %agg.result, [1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 { 838 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 839 %2 = bitcast i8* %1 to <4 x double>* 840 %3 = load <4 x double>* %2, align 8 841 %4 = bitcast <3 x double>* %agg.result to <4 x double>* 842 store <4 x double> %3, <4 x double>* %4, align 32, !tbaa !59 843 ret void 844 } 845 define <2 x double> @__rsAllocationVLoadXImpl_double2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 846 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 847 %2 = bitcast i8* %1 to <2 x double>* 848 %3 = load <2 x double>* %2, align 8 849 ret <2 x double> %3 850 } 851 852 853 define void @__rsAllocationVStoreXImpl_long4([1 x i32] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 854 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 855 %2 = bitcast i8* %1 to <4 x i64>* 856 store <4 x i64> %val, <4 x i64>* %2, align 8 857 ret void 858 } 859 define void @__rsAllocationVStoreXImpl_long3([1 x i32] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 860 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 861 %2 = bitcast i8* %1 to <3 x i64>* 862 store <3 x i64> %val, <3 x i64>* %2, align 8 863 ret void 864 } 865 define void @__rsAllocationVStoreXImpl_long2([1 x i32] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 866 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 867 %2 = bitcast i8* %1 to <2 x i64>* 868 store <2 x i64> %val, <2 x i64>* %2, align 8 869 ret void 870 } 871 872 define void @__rsAllocationVStoreXImpl_ulong4([1 x i32] %a.coerce, <4 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 873 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 874 %2 = bitcast i8* %1 to <4 x i64>* 875 store <4 x i64> %val, <4 x i64>* %2, align 8 876 ret void 877 } 878 define void @__rsAllocationVStoreXImpl_ulong3([1 x i32] %a.coerce, <3 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 879 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 880 %2 = bitcast i8* %1 to <3 x i64>* 881 store <3 x i64> %val, <3 x i64>* %2, align 8 882 ret void 883 } 884 define void @__rsAllocationVStoreXImpl_ulong2([1 x i32] %a.coerce, <2 x i64> %val, i32 %x, i32 %y, i32 %z) #1 { 885 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 886 %2 = bitcast i8* %1 to <2 x i64>* 887 store <2 x i64> %val, <2 x i64>* %2, align 8 888 ret void 889 } 890 891 define void @__rsAllocationVStoreXImpl_int4([1 x i32] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 892 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 893 %2 = bitcast i8* %1 to <4 x i32>* 894 store <4 x i32> %val, <4 x i32>* %2, align 4 895 ret void 896 } 897 define void @__rsAllocationVStoreXImpl_int3([1 x i32] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 898 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 899 %2 = bitcast i8* %1 to <3 x i32>* 900 store <3 x i32> %val, <3 x i32>* %2, align 4 901 ret void 902 } 903 define void @__rsAllocationVStoreXImpl_int2([1 x i32] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 904 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 905 %2 = bitcast i8* %1 to <2 x i32>* 906 store <2 x i32> %val, <2 x i32>* %2, align 4 907 ret void 908 } 909 910 define void @__rsAllocationVStoreXImpl_uint4([1 x i32] %a.coerce, <4 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 911 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 912 %2 = bitcast i8* %1 to <4 x i32>* 913 store <4 x i32> %val, <4 x i32>* %2, align 4 914 ret void 915 } 916 define void @__rsAllocationVStoreXImpl_uint3([1 x i32] %a.coerce, <3 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 917 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 918 %2 = bitcast i8* %1 to <3 x i32>* 919 store <3 x i32> %val, <3 x i32>* %2, align 4 920 ret void 921 } 922 define void @__rsAllocationVStoreXImpl_uint2([1 x i32] %a.coerce, <2 x i32> %val, i32 %x, i32 %y, i32 %z) #1 { 923 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 924 %2 = bitcast i8* %1 to <2 x i32>* 925 store <2 x i32> %val, <2 x i32>* %2, align 4 926 ret void 927 } 928 929 define void @__rsAllocationVStoreXImpl_short4([1 x i32] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 930 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 931 %2 = bitcast i8* %1 to <4 x i16>* 932 store <4 x i16> %val, <4 x i16>* %2, align 2 933 ret void 934 } 935 define void @__rsAllocationVStoreXImpl_short3([1 x i32] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 936 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 937 %2 = bitcast i8* %1 to <3 x i16>* 938 store <3 x i16> %val, <3 x i16>* %2, align 2 939 ret void 940 } 941 define void @__rsAllocationVStoreXImpl_short2([1 x i32] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 942 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 943 %2 = bitcast i8* %1 to <2 x i16>* 944 store <2 x i16> %val, <2 x i16>* %2, align 2 945 ret void 946 } 947 948 define void @__rsAllocationVStoreXImpl_ushort4([1 x i32] %a.coerce, <4 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 949 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 950 %2 = bitcast i8* %1 to <4 x i16>* 951 store <4 x i16> %val, <4 x i16>* %2, align 2 952 ret void 953 } 954 define void @__rsAllocationVStoreXImpl_ushort3([1 x i32] %a.coerce, <3 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 955 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 956 %2 = bitcast i8* %1 to <3 x i16>* 957 store <3 x i16> %val, <3 x i16>* %2, align 2 958 ret void 959 } 960 define void @__rsAllocationVStoreXImpl_ushort2([1 x i32] %a.coerce, <2 x i16> %val, i32 %x, i32 %y, i32 %z) #1 { 961 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 962 %2 = bitcast i8* %1 to <2 x i16>* 963 store <2 x i16> %val, <2 x i16>* %2, align 2 964 ret void 965 } 966 967 define void @__rsAllocationVStoreXImpl_char4([1 x i32] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 968 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 969 %2 = bitcast i8* %1 to <4 x i8>* 970 store <4 x i8> %val, <4 x i8>* %2, align 1 971 ret void 972 } 973 define void @__rsAllocationVStoreXImpl_char3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 974 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 975 %2 = bitcast i8* %1 to <3 x i8>* 976 store <3 x i8> %val, <3 x i8>* %2, align 1 977 ret void 978 } 979 define void @__rsAllocationVStoreXImpl_char2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 980 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 981 %2 = bitcast i8* %1 to <2 x i8>* 982 store <2 x i8> %val, <2 x i8>* %2, align 1 983 ret void 984 } 985 986 define void @__rsAllocationVStoreXImpl_uchar4([1 x i32] %a.coerce, <4 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 987 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 988 %2 = bitcast i8* %1 to <4 x i8>* 989 store <4 x i8> %val, <4 x i8>* %2, align 1 990 ret void 991 } 992 define void @__rsAllocationVStoreXImpl_uchar3([1 x i32] %a.coerce, <3 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 993 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 994 %2 = bitcast i8* %1 to <3 x i8>* 995 store <3 x i8> %val, <3 x i8>* %2, align 1 996 ret void 997 } 998 define void @__rsAllocationVStoreXImpl_uchar2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #1 { 999 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1000 %2 = bitcast i8* %1 to <2 x i8>* 1001 store <2 x i8> %val, <2 x i8>* %2, align 1 1002 ret void 1003 } 1004 1005 define void @__rsAllocationVStoreXImpl_float4([1 x i32] %a.coerce, <4 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 1006 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1007 %2 = bitcast i8* %1 to <4 x float>* 1008 store <4 x float> %val, <4 x float>* %2, align 4 1009 ret void 1010 } 1011 define void @__rsAllocationVStoreXImpl_float3([1 x i32] %a.coerce, <3 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 1012 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1013 %2 = bitcast i8* %1 to <3 x float>* 1014 store <3 x float> %val, <3 x float>* %2, align 4 1015 ret void 1016 } 1017 define void @__rsAllocationVStoreXImpl_float2([1 x i32] %a.coerce, <2 x float> %val, i32 %x, i32 %y, i32 %z) #1 { 1018 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1019 %2 = bitcast i8* %1 to <2 x float>* 1020 store <2 x float> %val, <2 x float>* %2, align 4 1021 ret void 1022 } 1023 1024 define void @__rsAllocationVStoreXImpl_double4([1 x i32] %a.coerce, <4 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 1025 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1026 %2 = bitcast i8* %1 to <4 x double>* 1027 store <4 x double> %val, <4 x double>* %2, align 8 1028 ret void 1029 } 1030 define void @__rsAllocationVStoreXImpl_double3([1 x i32] %a.coerce, <3 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 1031 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1032 %2 = bitcast i8* %1 to <3 x double>* 1033 store <3 x double> %val, <3 x double>* %2, align 8 1034 ret void 1035 } 1036 define void @__rsAllocationVStoreXImpl_double2([1 x i32] %a.coerce, <2 x double> %val, i32 %x, i32 %y, i32 %z) #1 { 1037 %1 = tail call i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #2 1038 %2 = bitcast i8* %1 to <2 x double>* 1039 store <2 x double> %val, <2 x double>* %2, align 8 1040 ret void 1041 } 1042 1043 1044 attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1045 attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } 1046 attributes #2 = { nobuiltin } 1047 1048
