Lines Matching defs:Address
45 class Address {
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
142 bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
143 bool computeCallAddress(const Value *V, Address &Addr);
144 bool simplifyAddress(Address &Addr, MVT VT);
145 void addLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
149 bool tryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
184 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
186 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
507 // Computes the address to get to an object.
508 bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
528 // address spaces.
551 Address SavedAddr = Addr;
603 Addr.setKind(Address::FrameIndexBase);
622 Address Backup = Addr;
854 bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
951 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
976 // the alloca address into a register, set the base type back to register and
986 Addr.setKind(Address::RegBase);
1044 void AArch64FastISel::addLoadStoreOperands(Address &Addr,
1061 assert(Addr.isRegBase() && "Unexpected address kind.");
1676 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1874 // See if we can handle this address.
1875 Address Addr;
1960 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
2054 // See if we can handle this address.
2055 Address Addr;
3000 Address Addr;
3001 Addr.setKind(Address::RegBase);
3111 Address Addr;
3182 bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
3189 Address OrigDest = Dest;
3190 Address OrigSrc = Src;
3339 // Recursively load frame address
3372 Address Dest, Src;
3386 // address spaces.
3403 // address spaces.
