Lines Matching defs:Load
284 // a load-and-extend of a f80 constant (in cases where the constant
311 // We want to use MVC in preference to even a single load/store pair.
350 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
750 // Create the SelectionDAG nodes corresponding to a load
1204 // load and a constant.
1206 C.Op0.getOpcode() != ISD::LOAD ||
1210 // We must have an 8- or 16-bit load.
1211 auto *Load = cast<LoadSDNode>(C.Op0);
1212 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1216 // The load must be an extending one and the constant must be within the
1221 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1244 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1257 Load->getExtensionType() != ExtType)
1258 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1259 Load->getChain(), Load->getBasePtr(),
1260 Load->getPointerInfo(), Load->getMemoryVT(),
1261 Load->isVolatile(), Load->isNonTemporal(),
1262 Load->isInvariant(), Load->getAlignment());
1270 // Return true if Op is either an unextended load, or a load suitable
1273 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1274 if (Load) {
1276 if (Load->getMemoryVT() == MVT::i8)
1279 switch (Load->getExtensionType()) {
1300 // zero can use LOAD TEST and comparisons with other constants make a
1316 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1381 // negation to set CC, so avoiding separate LOAD AND TEST and
1382 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1425 // If C compares the truncation of an extending load, try to compare
1430 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
2026 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2041 // Load the GOT offset of the module ID.
2073 // Load the offset from the GOT.
2084 // Force the offset into the constant pool and load it from there.
2118 // Use LARL to load the address of the table.
2135 // Use LARL to load the address of the constant pool entry.
2458 // Op is an atomic load. Lower it into a normal volatile load.
3616 // The load of R0L can be hoisted by post-RA LICM.
