Home | History | Annotate | Download | only in Mips 
      1 //===-- MipsInstrInfo.cpp - Mips Instruction Information ------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the Mips implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "MipsInstrInfo.h"
     15 #include "InstPrinter/MipsInstPrinter.h"
     16 #include "MipsAnalyzeImmediate.h"
     17 #include "MipsMachineFunction.h"
     18 #include "MipsSubtarget.h"
     19 #include "llvm/ADT/STLExtras.h"
     20 #include "llvm/CodeGen/MachineInstrBuilder.h"
     21 #include "llvm/CodeGen/MachineRegisterInfo.h"
     22 #include "llvm/Support/ErrorHandling.h"
     23 #include "llvm/Support/TargetRegistry.h"
     24 
     25 using namespace llvm;
     26 
     27 #define GET_INSTRINFO_CTOR_DTOR
     28 #include "MipsGenInstrInfo.inc"
     29 
     30 // Pin the vtable to this file.
     31 void MipsInstrInfo::anchor() {}
     32 
     33 MipsInstrInfo::MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBr)
     34     : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     35       Subtarget(STI), UncondBrOpc(UncondBr) {}
     36 
     37 const MipsInstrInfo *MipsInstrInfo::create(MipsSubtarget &STI) {
     38   if (STI.inMips16Mode())
     39     return llvm::createMips16InstrInfo(STI);
     40 
     41   return llvm::createMipsSEInstrInfo(STI);
     42 }
     43 
     44 bool MipsInstrInfo::isZeroImm(const MachineOperand &op) const {
     45   return op.isImm() && op.getImm() == 0;
     46 }
     47 
     48 /// insertNoop - If data hazard condition is found insert the target nop
     49 /// instruction.
     50 void MipsInstrInfo::
     51 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
     52 {
     53   DebugLoc DL;
     54   BuildMI(MBB, MI, DL, get(Mips::NOP));
     55 }
     56 
     57 MachineMemOperand *MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI,
     58                                                 unsigned Flag) const {
     59   MachineFunction &MF = *MBB.getParent();
     60   MachineFrameInfo &MFI = *MF.getFrameInfo();
     61   unsigned Align = MFI.getObjectAlignment(FI);
     62 
     63   return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
     64                                  MFI.getObjectSize(FI), Align);
     65 }
     66 
     67 //===----------------------------------------------------------------------===//
     68 // Branch Analysis
     69 //===----------------------------------------------------------------------===//
     70 
     71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
     72                                   MachineBasicBlock *&BB,
     73                                   SmallVectorImpl<MachineOperand> &Cond) const {
     74   assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
     75   int NumOp = Inst->getNumExplicitOperands();
     76 
     77   // for both int and fp branches, the last explicit operand is the
     78   // MBB.
     79   BB = Inst->getOperand(NumOp-1).getMBB();
     80   Cond.push_back(MachineOperand::CreateImm(Opc));
     81 
     82   for (int i=0; i<NumOp-1; i++)
     83     Cond.push_back(Inst->getOperand(i));
     84 }
     85 
     86 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
     87                                   MachineBasicBlock *&TBB,
     88                                   MachineBasicBlock *&FBB,
     89                                   SmallVectorImpl<MachineOperand> &Cond,
     90                                   bool AllowModify) const {
     91   SmallVector<MachineInstr*, 2> BranchInstrs;
     92   BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs);
     93 
     94   return (BT == BT_None) || (BT == BT_Indirect);
     95 }
     96 
     97 void
     98 MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
     99                            DebugLoc DL,
    100                            const SmallVectorImpl<MachineOperand> &Cond) const {
    101   unsigned Opc = Cond[0].getImm();
    102   const MCInstrDesc &MCID = get(Opc);
    103   MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
    104 
    105   for (unsigned i = 1; i < Cond.size(); ++i) {
    106     if (Cond[i].isReg())
    107       MIB.addReg(Cond[i].getReg());
    108     else if (Cond[i].isImm())
    109       MIB.addImm(Cond[i].getImm());
    110     else
    111        assert(true && "Cannot copy operand");
    112   }
    113   MIB.addMBB(TBB);
    114 }
    115 
    116 unsigned MipsInstrInfo::InsertBranch(
    117     MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
    118     const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
    119   // Shouldn't be a fall through.
    120   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
    121 
    122   // # of condition operands:
    123   //  Unconditional branches: 0
    124   //  Floating point branches: 1 (opc)
    125   //  Int BranchZero: 2 (opc, reg)
    126   //  Int Branch: 3 (opc, reg0, reg1)
    127   assert((Cond.size() <= 3) &&
    128          "# of Mips branch conditions must be <= 3!");
    129 
    130   // Two-way Conditional branch.
    131   if (FBB) {
    132     BuildCondBr(MBB, TBB, DL, Cond);
    133     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
    134     return 2;
    135   }
    136 
    137   // One way branch.
    138   // Unconditional branch.
    139   if (Cond.empty())
    140     BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
    141   else // Conditional branch.
    142     BuildCondBr(MBB, TBB, DL, Cond);
    143   return 1;
    144 }
    145 
    146 unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
    147   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    148   MachineBasicBlock::reverse_iterator FirstBr;
    149   unsigned removed;
    150 
    151   // Skip all the debug instructions.
    152   while (I != REnd && I->isDebugValue())
    153     ++I;
    154 
    155   FirstBr = I;
    156 
    157   // Up to 2 branches are removed.
    158   // Note that indirect branches are not removed.
    159   for (removed = 0; I != REnd && removed < 2; ++I, ++removed)
    160     if (!getAnalyzableBrOpc(I->getOpcode()))
    161       break;
    162 
    163   MBB.erase(I.base(), FirstBr.base());
    164 
    165   return removed;
    166 }
    167 
    168 /// ReverseBranchCondition - Return the inverse opcode of the
    169 /// specified Branch instruction.
    170 bool MipsInstrInfo::ReverseBranchCondition(
    171     SmallVectorImpl<MachineOperand> &Cond) const {
    172   assert( (Cond.size() && Cond.size() <= 3) &&
    173           "Invalid Mips branch condition!");
    174   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
    175   return false;
    176 }
    177 
    178 MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch(
    179     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
    180     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify,
    181     SmallVectorImpl<MachineInstr *> &BranchInstrs) const {
    182 
    183   MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend();
    184 
    185   // Skip all the debug instructions.
    186   while (I != REnd && I->isDebugValue())
    187     ++I;
    188 
    189   if (I == REnd || !isUnpredicatedTerminator(&*I)) {
    190     // This block ends with no branches (it just falls through to its succ).
    191     // Leave TBB/FBB null.
    192     TBB = FBB = nullptr;
    193     return BT_NoBranch;
    194   }
    195 
    196   MachineInstr *LastInst = &*I;
    197   unsigned LastOpc = LastInst->getOpcode();
    198   BranchInstrs.push_back(LastInst);
    199 
    200   // Not an analyzable branch (e.g., indirect jump).
    201   if (!getAnalyzableBrOpc(LastOpc))
    202     return LastInst->isIndirectBranch() ? BT_Indirect : BT_None;
    203 
    204   // Get the second to last instruction in the block.
    205   unsigned SecondLastOpc = 0;
    206   MachineInstr *SecondLastInst = nullptr;
    207 
    208   if (++I != REnd) {
    209     SecondLastInst = &*I;
    210     SecondLastOpc = getAnalyzableBrOpc(SecondLastInst->getOpcode());
    211 
    212     // Not an analyzable branch (must be an indirect jump).
    213     if (isUnpredicatedTerminator(SecondLastInst) && !SecondLastOpc)
    214       return BT_None;
    215   }
    216 
    217   // If there is only one terminator instruction, process it.
    218   if (!SecondLastOpc) {
    219     // Unconditional branch.
    220     if (LastOpc == UncondBrOpc) {
    221       TBB = LastInst->getOperand(0).getMBB();
    222       return BT_Uncond;
    223     }
    224 
    225     // Conditional branch
    226     AnalyzeCondBr(LastInst, LastOpc, TBB, Cond);
    227     return BT_Cond;
    228   }
    229 
    230   // If we reached here, there are two branches.
    231   // If there are three terminators, we don't know what sort of block this is.
    232   if (++I != REnd && isUnpredicatedTerminator(&*I))
    233     return BT_None;
    234 
    235   BranchInstrs.insert(BranchInstrs.begin(), SecondLastInst);
    236 
    237   // If second to last instruction is an unconditional branch,
    238   // analyze it and remove the last instruction.
    239   if (SecondLastOpc == UncondBrOpc) {
    240     // Return if the last instruction cannot be removed.
    241     if (!AllowModify)
    242       return BT_None;
    243 
    244     TBB = SecondLastInst->getOperand(0).getMBB();
    245     LastInst->eraseFromParent();
    246     BranchInstrs.pop_back();
    247     return BT_Uncond;
    248   }
    249 
    250   // Conditional branch followed by an unconditional branch.
    251   // The last one must be unconditional.
    252   if (LastOpc != UncondBrOpc)
    253     return BT_None;
    254 
    255   AnalyzeCondBr(SecondLastInst, SecondLastOpc, TBB, Cond);
    256   FBB = LastInst->getOperand(0).getMBB();
    257 
    258   return BT_CondUncond;
    259 }
    260 
    261 /// Return the number of bytes of code the specified instruction may be.
    262 unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
    263   switch (MI->getOpcode()) {
    264   default:
    265     return MI->getDesc().getSize();
    266   case  TargetOpcode::INLINEASM: {       // Inline Asm: Variable size.
    267     const MachineFunction *MF = MI->getParent()->getParent();
    268     const char *AsmStr = MI->getOperand(0).getSymbolName();
    269     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
    270   }
    271   case Mips::CONSTPOOL_ENTRY:
    272     // If this machine instr is a constant pool entry, its size is recorded as
    273     // operand #2.
    274     return MI->getOperand(2).getImm();
    275   }
    276 }
    277 
    278 MachineInstrBuilder
    279 MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc,
    280                                   MachineBasicBlock::iterator I) const {
    281   MachineInstrBuilder MIB;
    282   MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), get(NewOpc));
    283 
    284   for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J)
    285     MIB.addOperand(I->getOperand(J));
    286 
    287   MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end());
    288   return MIB;
    289 }
    290