1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H 15 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H 16 17 #include "MCTargetDesc/X86BaseInfo.h" 18 #include "X86RegisterInfo.h" 19 #include "llvm/ADT/DenseMap.h" 20 #include "llvm/Target/TargetInstrInfo.h" 21 22 #define GET_INSTRINFO_HEADER 23 #include "X86GenInstrInfo.inc" 24 25 namespace llvm { 26 class X86RegisterInfo; 27 class X86Subtarget; 28 29 namespace X86 { 30 // X86 specific condition code. These correspond to X86_*_COND in 31 // X86InstrInfo.td. They must be kept in synch. 32 enum CondCode { 33 COND_A = 0, 34 COND_AE = 1, 35 COND_B = 2, 36 COND_BE = 3, 37 COND_E = 4, 38 COND_G = 5, 39 COND_GE = 6, 40 COND_L = 7, 41 COND_LE = 8, 42 COND_NE = 9, 43 COND_NO = 10, 44 COND_NP = 11, 45 COND_NS = 12, 46 COND_O = 13, 47 COND_P = 14, 48 COND_S = 15, 49 LAST_VALID_COND = COND_S, 50 51 // Artificial condition codes. These are used by AnalyzeBranch 52 // to indicate a block terminated with two conditional branches to 53 // the same location. This occurs in code using FCMP_OEQ or FCMP_UNE, 54 // which can't be represented on x86 with a single condition. These 55 // are never used in MachineInstrs. 56 COND_NE_OR_P, 57 COND_NP_OR_E, 58 59 COND_INVALID 60 }; 61 62 // Turn condition code into conditional branch opcode. 63 unsigned GetCondBranchFromCond(CondCode CC); 64 65 /// \brief Return a set opcode for the given condition and whether it has 66 /// a memory operand. 67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false); 68 69 /// \brief Return a cmov opcode for the given condition, register size in 70 /// bytes, and operand type. 71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes, 72 bool HasMemoryOperand = false); 73 74 // Turn CMov opcode into condition code. 75 CondCode getCondFromCMovOpc(unsigned Opc); 76 77 /// GetOppositeBranchCondition - Return the inverse of the specified cond, 78 /// e.g. turning COND_E to COND_NE. 79 CondCode GetOppositeBranchCondition(CondCode CC); 80 } // end namespace X86; 81 82 83 /// isGlobalStubReference - Return true if the specified TargetFlag operand is 84 /// a reference to a stub for a global, not the global itself. 85 inline static bool isGlobalStubReference(unsigned char TargetFlag) { 86 switch (TargetFlag) { 87 case X86II::MO_DLLIMPORT: // dllimport stub. 88 case X86II::MO_GOTPCREL: // rip-relative GOT reference. 89 case X86II::MO_GOT: // normal GOT reference. 90 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref. 91 case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref. 92 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref. 93 return true; 94 default: 95 return false; 96 } 97 } 98 99 /// isGlobalRelativeToPICBase - Return true if the specified global value 100 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this 101 /// is true, the addressing mode has the PIC base register added in (e.g. EBX). 102 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) { 103 switch (TargetFlag) { 104 case X86II::MO_GOTOFF: // isPICStyleGOT: local global. 105 case X86II::MO_GOT: // isPICStyleGOT: other global. 106 case X86II::MO_PIC_BASE_OFFSET: // Darwin local global. 107 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global. 108 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global. 109 case X86II::MO_TLVP: // ??? Pretty sure.. 110 return true; 111 default: 112 return false; 113 } 114 } 115 116 inline static bool isScale(const MachineOperand &MO) { 117 return MO.isImm() && 118 (MO.getImm() == 1 || MO.getImm() == 2 || 119 MO.getImm() == 4 || MO.getImm() == 8); 120 } 121 122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { 123 if (MI->getOperand(Op).isFI()) return true; 124 return Op+X86::AddrSegmentReg <= MI->getNumOperands() && 125 MI->getOperand(Op+X86::AddrBaseReg).isReg() && 126 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) && 127 MI->getOperand(Op+X86::AddrIndexReg).isReg() && 128 (MI->getOperand(Op+X86::AddrDisp).isImm() || 129 MI->getOperand(Op+X86::AddrDisp).isGlobal() || 130 MI->getOperand(Op+X86::AddrDisp).isCPI() || 131 MI->getOperand(Op+X86::AddrDisp).isJTI()); 132 } 133 134 inline static bool isMem(const MachineInstr *MI, unsigned Op) { 135 if (MI->getOperand(Op).isFI()) return true; 136 return Op+X86::AddrNumOperands <= MI->getNumOperands() && 137 MI->getOperand(Op+X86::AddrSegmentReg).isReg() && 138 isLeaMem(MI, Op); 139 } 140 141 class X86InstrInfo final : public X86GenInstrInfo { 142 X86Subtarget &Subtarget; 143 const X86RegisterInfo RI; 144 145 /// RegOp2MemOpTable3Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, 146 /// RegOp2MemOpTable2, RegOp2MemOpTable3 - Load / store folding opcode maps. 147 /// 148 typedef DenseMap<unsigned, 149 std::pair<unsigned, unsigned> > RegOp2MemOpTableType; 150 RegOp2MemOpTableType RegOp2MemOpTable2Addr; 151 RegOp2MemOpTableType RegOp2MemOpTable0; 152 RegOp2MemOpTableType RegOp2MemOpTable1; 153 RegOp2MemOpTableType RegOp2MemOpTable2; 154 RegOp2MemOpTableType RegOp2MemOpTable3; 155 RegOp2MemOpTableType RegOp2MemOpTable4; 156 157 /// MemOp2RegOpTable - Load / store unfolding opcode map. 158 /// 159 typedef DenseMap<unsigned, 160 std::pair<unsigned, unsigned> > MemOp2RegOpTableType; 161 MemOp2RegOpTableType MemOp2RegOpTable; 162 163 static void AddTableEntry(RegOp2MemOpTableType &R2MTable, 164 MemOp2RegOpTableType &M2RTable, 165 unsigned RegOp, unsigned MemOp, unsigned Flags); 166 167 virtual void anchor(); 168 169 public: 170 explicit X86InstrInfo(X86Subtarget &STI); 171 172 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 173 /// such, whenever a client has an instance of instruction info, it should 174 /// always be able to get register info as well (through this method). 175 /// 176 const X86RegisterInfo &getRegisterInfo() const { return RI; } 177 178 /// getSPAdjust - This returns the stack pointer adjustment made by 179 /// this instruction. For x86, we need to handle more complex call 180 /// sequences involving PUSHes. 181 int getSPAdjust(const MachineInstr *MI) const override; 182 183 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" 184 /// extension instruction. That is, it's like a copy where it's legal for the 185 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns 186 /// true, then it's expected the pre-extension value is available as a subreg 187 /// of the result register. This also returns the sub-register index in 188 /// SubIdx. 189 bool isCoalescableExtInstr(const MachineInstr &MI, 190 unsigned &SrcReg, unsigned &DstReg, 191 unsigned &SubIdx) const override; 192 193 unsigned isLoadFromStackSlot(const MachineInstr *MI, 194 int &FrameIndex) const override; 195 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination 196 /// stack locations as well. This uses a heuristic so it isn't 197 /// reliable for correctness. 198 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 199 int &FrameIndex) const override; 200 201 unsigned isStoreToStackSlot(const MachineInstr *MI, 202 int &FrameIndex) const override; 203 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination 204 /// stack locations as well. This uses a heuristic so it isn't 205 /// reliable for correctness. 206 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI, 207 int &FrameIndex) const override; 208 209 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 210 AliasAnalysis *AA) const override; 211 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 212 unsigned DestReg, unsigned SubIdx, 213 const MachineInstr *Orig, 214 const TargetRegisterInfo &TRI) const override; 215 216 /// Given an operand within a MachineInstr, insert preceding code to put it 217 /// into the right format for a particular kind of LEA instruction. This may 218 /// involve using an appropriate super-register instead (with an implicit use 219 /// of the original) or creating a new virtual register and inserting COPY 220 /// instructions to get the data into the right class. 221 /// 222 /// Reference parameters are set to indicate how caller should add this 223 /// operand to the LEA instruction. 224 bool classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, 225 unsigned LEAOpcode, bool AllowSP, 226 unsigned &NewSrc, bool &isKill, 227 bool &isUndef, MachineOperand &ImplicitOp) const; 228 229 /// convertToThreeAddress - This method must be implemented by targets that 230 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 231 /// may be able to convert a two-address instruction into a true 232 /// three-address instruction on demand. This allows the X86 target (for 233 /// example) to convert ADD and SHL instructions into LEA instructions if they 234 /// would require register copies due to two-addressness. 235 /// 236 /// This method returns a null pointer if the transformation cannot be 237 /// performed, otherwise it returns the new instruction. 238 /// 239 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, 240 MachineBasicBlock::iterator &MBBI, 241 LiveVariables *LV) const override; 242 243 /// commuteInstruction - We have a few instructions that must be hacked on to 244 /// commute them. 245 /// 246 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override; 247 248 bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, 249 unsigned &SrcOpIdx2) const override; 250 251 // Branch analysis. 252 bool isUnpredicatedTerminator(const MachineInstr* MI) const override; 253 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 254 MachineBasicBlock *&FBB, 255 SmallVectorImpl<MachineOperand> &Cond, 256 bool AllowModify) const override; 257 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 258 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 259 MachineBasicBlock *FBB, 260 const SmallVectorImpl<MachineOperand> &Cond, 261 DebugLoc DL) const override; 262 bool canInsertSelect(const MachineBasicBlock&, 263 const SmallVectorImpl<MachineOperand> &Cond, 264 unsigned, unsigned, int&, int&, int&) const override; 265 void insertSelect(MachineBasicBlock &MBB, 266 MachineBasicBlock::iterator MI, DebugLoc DL, 267 unsigned DstReg, 268 const SmallVectorImpl<MachineOperand> &Cond, 269 unsigned TrueReg, unsigned FalseReg) const override; 270 void copyPhysReg(MachineBasicBlock &MBB, 271 MachineBasicBlock::iterator MI, DebugLoc DL, 272 unsigned DestReg, unsigned SrcReg, 273 bool KillSrc) const override; 274 void storeRegToStackSlot(MachineBasicBlock &MBB, 275 MachineBasicBlock::iterator MI, 276 unsigned SrcReg, bool isKill, int FrameIndex, 277 const TargetRegisterClass *RC, 278 const TargetRegisterInfo *TRI) const override; 279 280 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 281 SmallVectorImpl<MachineOperand> &Addr, 282 const TargetRegisterClass *RC, 283 MachineInstr::mmo_iterator MMOBegin, 284 MachineInstr::mmo_iterator MMOEnd, 285 SmallVectorImpl<MachineInstr*> &NewMIs) const; 286 287 void loadRegFromStackSlot(MachineBasicBlock &MBB, 288 MachineBasicBlock::iterator MI, 289 unsigned DestReg, int FrameIndex, 290 const TargetRegisterClass *RC, 291 const TargetRegisterInfo *TRI) const override; 292 293 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 294 SmallVectorImpl<MachineOperand> &Addr, 295 const TargetRegisterClass *RC, 296 MachineInstr::mmo_iterator MMOBegin, 297 MachineInstr::mmo_iterator MMOEnd, 298 SmallVectorImpl<MachineInstr*> &NewMIs) const; 299 300 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 301 302 /// foldMemoryOperand - If this target supports it, fold a load or store of 303 /// the specified stack slot into the specified machine instruction for the 304 /// specified operand(s). If this is possible, the target should perform the 305 /// folding and return true, otherwise it should return false. If it folds 306 /// the instruction, it is likely that the MachineInstruction the iterator 307 /// references has been changed. 308 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 309 ArrayRef<unsigned> Ops, 310 int FrameIndex) const override; 311 312 /// foldMemoryOperand - Same as the previous version except it allows folding 313 /// of any load and store from / to any address, not just from a specific 314 /// stack slot. 315 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 316 ArrayRef<unsigned> Ops, 317 MachineInstr *LoadMI) const override; 318 319 /// canFoldMemoryOperand - Returns true if the specified load / store is 320 /// folding is possible. 321 bool canFoldMemoryOperand(const MachineInstr *, 322 ArrayRef<unsigned>) const override; 323 324 /// unfoldMemoryOperand - Separate a single instruction which folded a load or 325 /// a store or a load and a store into two or more instruction. If this is 326 /// possible, returns true as well as the new instructions by reference. 327 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 328 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 329 SmallVectorImpl<MachineInstr*> &NewMIs) const override; 330 331 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 332 SmallVectorImpl<SDNode*> &NewNodes) const override; 333 334 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new 335 /// instruction after load / store are unfolded from an instruction of the 336 /// specified opcode. It returns zero if the specified unfolding is not 337 /// possible. If LoadRegIndex is non-null, it is filled in with the operand 338 /// index of the operand which will hold the register holding the loaded 339 /// value. 340 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 341 bool UnfoldLoad, bool UnfoldStore, 342 unsigned *LoadRegIndex = nullptr) const override; 343 344 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler 345 /// to determine if two loads are loading from the same base address. It 346 /// should only return true if the base pointers are the same and the 347 /// only differences between the two addresses are the offset. It also returns 348 /// the offsets by reference. 349 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, 350 int64_t &Offset2) const override; 351 352 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to 353 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should 354 /// be scheduled togther. On some targets if two loads are loading from 355 /// addresses in the same cache line, it's better if they are scheduled 356 /// together. This function takes two integers that represent the load offsets 357 /// from the common base address. It returns true if it decides it's desirable 358 /// to schedule the two loads together. "NumLoads" is the number of loads that 359 /// have already been scheduled after Load1. 360 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 361 int64_t Offset1, int64_t Offset2, 362 unsigned NumLoads) const override; 363 364 bool shouldScheduleAdjacent(MachineInstr* First, 365 MachineInstr *Second) const override; 366 367 void getNoopForMachoTarget(MCInst &NopInst) const override; 368 369 bool 370 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 371 372 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine 373 /// instruction that defines the specified register class. 374 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; 375 376 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha 377 /// would clobber the EFLAGS condition register. Note the result may be 378 /// conservative. If it cannot definitely determine the safety after visiting 379 /// a few instructions in each direction it assumes it's not safe. 380 bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 381 MachineBasicBlock::iterator I) const; 382 383 static bool isX86_64ExtendedReg(const MachineOperand &MO) { 384 if (!MO.isReg()) return false; 385 return X86II::isX86_64ExtendedReg(MO.getReg()); 386 } 387 388 /// getGlobalBaseReg - Return a virtual register initialized with the 389 /// the global base register value. Output instructions required to 390 /// initialize the register in the function entry block, if necessary. 391 /// 392 unsigned getGlobalBaseReg(MachineFunction *MF) const; 393 394 std::pair<uint16_t, uint16_t> 395 getExecutionDomain(const MachineInstr *MI) const override; 396 397 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override; 398 399 unsigned 400 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, 401 const TargetRegisterInfo *TRI) const override; 402 unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, 403 const TargetRegisterInfo *TRI) const override; 404 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, 405 const TargetRegisterInfo *TRI) const override; 406 407 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 408 unsigned OpNum, 409 ArrayRef<MachineOperand> MOs, 410 unsigned Size, unsigned Alignment, 411 bool AllowCommute) const; 412 413 void 414 getUnconditionalBranch(MCInst &Branch, 415 const MCSymbolRefExpr *BranchTarget) const override; 416 417 void getTrap(MCInst &MI) const override; 418 419 unsigned getJumpInstrTableEntryBound() const override; 420 421 bool isHighLatencyDef(int opc) const override; 422 423 bool hasHighOperandLatency(const InstrItineraryData *ItinData, 424 const MachineRegisterInfo *MRI, 425 const MachineInstr *DefMI, unsigned DefIdx, 426 const MachineInstr *UseMI, 427 unsigned UseIdx) const override; 428 429 /// analyzeCompare - For a comparison instruction, return the source registers 430 /// in SrcReg and SrcReg2 if having two register operands, and the value it 431 /// compares against in CmpValue. Return true if the comparison instruction 432 /// can be analyzed. 433 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, 434 unsigned &SrcReg2, int &CmpMask, 435 int &CmpValue) const override; 436 437 /// optimizeCompareInstr - Check if there exists an earlier instruction that 438 /// operates on the same source operands and sets flags in the same way as 439 /// Compare; remove Compare if possible. 440 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, 441 unsigned SrcReg2, int CmpMask, int CmpValue, 442 const MachineRegisterInfo *MRI) const override; 443 444 /// optimizeLoadInstr - Try to remove the load by folding it to a register 445 /// operand at the use. We fold the load instructions if and only if the 446 /// def and use are in the same BB. We only look at one load and see 447 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register 448 /// defined by the load we are trying to fold. DefMI returns the machine 449 /// instruction that defines FoldAsLoadDefReg, and the function returns 450 /// the machine instruction generated due to folding. 451 MachineInstr* optimizeLoadInstr(MachineInstr *MI, 452 const MachineRegisterInfo *MRI, 453 unsigned &FoldAsLoadDefReg, 454 MachineInstr *&DefMI) const override; 455 456 private: 457 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc, 458 MachineFunction::iterator &MFI, 459 MachineBasicBlock::iterator &MBBI, 460 LiveVariables *LV) const; 461 462 /// isFrameOperand - Return true and the FrameIndex if the specified 463 /// operand and follow operands form a reference to the stack frame. 464 bool isFrameOperand(const MachineInstr *MI, unsigned int Op, 465 int &FrameIndex) const; 466 }; 467 468 } // End llvm namespace 469 470 #endif 471
