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      1 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines an instruction selector for the SPARC target.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "SparcTargetMachine.h"
     15 #include "llvm/CodeGen/SelectionDAGISel.h"
     16 #include "llvm/IR/Intrinsics.h"
     17 #include "llvm/Support/Compiler.h"
     18 #include "llvm/Support/Debug.h"
     19 #include "llvm/Support/ErrorHandling.h"
     20 #include "llvm/Support/raw_ostream.h"
     21 using namespace llvm;
     22 
     23 //===----------------------------------------------------------------------===//
     24 // Instruction Selector Implementation
     25 //===----------------------------------------------------------------------===//
     26 
     27 //===--------------------------------------------------------------------===//
     28 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
     29 /// instructions for SelectionDAG operations.
     30 ///
     31 namespace {
     32 class SparcDAGToDAGISel : public SelectionDAGISel {
     33   /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
     34   /// make the right decision when generating code for different targets.
     35   const SparcSubtarget *Subtarget;
     36 public:
     37   explicit SparcDAGToDAGISel(SparcTargetMachine &tm) : SelectionDAGISel(tm) {}
     38 
     39   bool runOnMachineFunction(MachineFunction &MF) override {
     40     Subtarget = &MF.getSubtarget<SparcSubtarget>();
     41     return SelectionDAGISel::runOnMachineFunction(MF);
     42   }
     43 
     44   SDNode *Select(SDNode *N) override;
     45 
     46   // Complex Pattern Selectors.
     47   bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
     48   bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
     49 
     50   /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
     51   /// inline asm expressions.
     52   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
     53                                     unsigned ConstraintID,
     54                                     std::vector<SDValue> &OutOps) override;
     55 
     56   const char *getPassName() const override {
     57     return "SPARC DAG->DAG Pattern Instruction Selection";
     58   }
     59 
     60   // Include the pieces autogenerated from the target description.
     61 #include "SparcGenDAGISel.inc"
     62 
     63 private:
     64   SDNode* getGlobalBaseReg();
     65 };
     66 }  // end anonymous namespace
     67 
     68 SDNode* SparcDAGToDAGISel::getGlobalBaseReg() {
     69   unsigned GlobalBaseReg = Subtarget->getInstrInfo()->getGlobalBaseReg(MF);
     70   return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy()).getNode();
     71 }
     72 
     73 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
     74                                      SDValue &Base, SDValue &Offset) {
     75   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
     76     Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy());
     77     Offset = CurDAG->getTargetConstant(0, MVT::i32);
     78     return true;
     79   }
     80   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
     81       Addr.getOpcode() == ISD::TargetGlobalAddress ||
     82       Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
     83     return false;  // direct calls.
     84 
     85   if (Addr.getOpcode() == ISD::ADD) {
     86     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
     87       if (isInt<13>(CN->getSExtValue())) {
     88         if (FrameIndexSDNode *FIN =
     89                 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
     90           // Constant offset from frame ref.
     91           Base =
     92               CurDAG->getTargetFrameIndex(FIN->getIndex(), TLI->getPointerTy());
     93         } else {
     94           Base = Addr.getOperand(0);
     95         }
     96         Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
     97         return true;
     98       }
     99     }
    100     if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
    101       Base = Addr.getOperand(1);
    102       Offset = Addr.getOperand(0).getOperand(0);
    103       return true;
    104     }
    105     if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
    106       Base = Addr.getOperand(0);
    107       Offset = Addr.getOperand(1).getOperand(0);
    108       return true;
    109     }
    110   }
    111   Base = Addr;
    112   Offset = CurDAG->getTargetConstant(0, MVT::i32);
    113   return true;
    114 }
    115 
    116 bool SparcDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
    117   if (Addr.getOpcode() == ISD::FrameIndex) return false;
    118   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
    119       Addr.getOpcode() == ISD::TargetGlobalAddress ||
    120       Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
    121     return false;  // direct calls.
    122 
    123   if (Addr.getOpcode() == ISD::ADD) {
    124     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
    125       if (isInt<13>(CN->getSExtValue()))
    126         return false;  // Let the reg+imm pattern catch this!
    127     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
    128         Addr.getOperand(1).getOpcode() == SPISD::Lo)
    129       return false;  // Let the reg+imm pattern catch this!
    130     R1 = Addr.getOperand(0);
    131     R2 = Addr.getOperand(1);
    132     return true;
    133   }
    134 
    135   R1 = Addr;
    136   R2 = CurDAG->getRegister(SP::G0, TLI->getPointerTy());
    137   return true;
    138 }
    139 
    140 SDNode *SparcDAGToDAGISel::Select(SDNode *N) {
    141   SDLoc dl(N);
    142   if (N->isMachineOpcode()) {
    143     N->setNodeId(-1);
    144     return nullptr;   // Already selected.
    145   }
    146 
    147   switch (N->getOpcode()) {
    148   default: break;
    149   case SPISD::GLOBAL_BASE_REG:
    150     return getGlobalBaseReg();
    151 
    152   case ISD::SDIV:
    153   case ISD::UDIV: {
    154     // sdivx / udivx handle 64-bit divides.
    155     if (N->getValueType(0) == MVT::i64)
    156       break;
    157     // FIXME: should use a custom expander to expose the SRA to the dag.
    158     SDValue DivLHS = N->getOperand(0);
    159     SDValue DivRHS = N->getOperand(1);
    160 
    161     // Set the Y register to the high-part.
    162     SDValue TopPart;
    163     if (N->getOpcode() == ISD::SDIV) {
    164       TopPart = SDValue(CurDAG->getMachineNode(SP::SRAri, dl, MVT::i32, DivLHS,
    165                                    CurDAG->getTargetConstant(31, MVT::i32)), 0);
    166     } else {
    167       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
    168     }
    169     TopPart = SDValue(CurDAG->getMachineNode(SP::WRYrr, dl, MVT::Glue, TopPart,
    170                                      CurDAG->getRegister(SP::G0, MVT::i32)), 0);
    171 
    172     // FIXME: Handle div by immediate.
    173     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
    174     return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
    175                                 TopPart);
    176   }
    177   case ISD::MULHU:
    178   case ISD::MULHS: {
    179     // FIXME: Handle mul by immediate.
    180     SDValue MulLHS = N->getOperand(0);
    181     SDValue MulRHS = N->getOperand(1);
    182     unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
    183     SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
    184                                          MulLHS, MulRHS);
    185     // The high part is in the Y register.
    186     return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
    187   }
    188   }
    189 
    190   return SelectCode(N);
    191 }
    192 
    193 
    194 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
    195 /// inline asm expressions.
    196 bool
    197 SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
    198                                                 unsigned ConstraintID,
    199                                                 std::vector<SDValue> &OutOps) {
    200   SDValue Op0, Op1;
    201   switch (ConstraintID) {
    202   default: return true;
    203   case InlineAsm::Constraint_i:
    204   case InlineAsm::Constraint_m: // memory
    205    if (!SelectADDRrr(Op, Op0, Op1))
    206      SelectADDRri(Op, Op0, Op1);
    207    break;
    208   }
    209 
    210   OutOps.push_back(Op0);
    211   OutOps.push_back(Op1);
    212   return false;
    213 }
    214 
    215 /// createSparcISelDag - This pass converts a legalized DAG into a
    216 /// SPARC-specific DAG, ready for instruction scheduling.
    217 ///
    218 FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
    219   return new SparcDAGToDAGISel(TM);
    220 }
    221