| /external/llvm/lib/Target/X86/ |
| X86RegisterInfo.h | 41 /// FramePtr - X86 physical register used as frame ptr.
43 unsigned FramePtr;
|
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 101 unsigned FramePtr)
107 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
127 .addReg(FramePtr);
145 .addReg(FramePtr);
169 unsigned FramePtr = SP::I6;
172 FramePtr = SP::O6;
185 .addReg(FramePtr).addImm(0).addReg(SrcEvenReg);
186 replaceFI(MF, II, *StMI, dl, 0, Offset, FramePtr);
197 .addReg(FramePtr).addImm(0);
198 replaceFI(MF, II, *StMI, dl, 1, Offset, FramePtr);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 103 unsigned FramePtr = RegInfo->getFrameRegister(MF);
159 if (Reg == FramePtr)
239 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
245 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
252 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
340 unsigned FramePtr = RegInfo->getFrameRegister(MF);
369 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
377 .addReg(FramePtr));
|
| ARMExpandPseudoInsts.cpp | [all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMFrameLowering.cpp | 300 unsigned FramePtr = RegInfo->getFrameRegister(MF);
359 if (Reg == FramePtr)
513 dl, TII, FramePtr, ARM::SP,
518 nullptr, MRI->getDwarfRegNum(FramePtr, true),
526 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
748 unsigned FramePtr = RegInfo->getFrameRegister(MF);
784 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
796 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
806 .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
810 .addReg(FramePtr));
[all...] |
| ARMFastISel.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| SjLjEHPrepare.cpp | 413 Value *FramePtr = Builder.CreateConstGEP2_32(doubleUnderJBufTy, JBufPtr, 0, 0,
417 Builder.CreateStore(Val, FramePtr, /*isVolatile=*/true);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 35 static const unsigned FramePtr = XCore::R10;
152 FramePtr));
306 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
309 MRI->getDwarfRegNum(FramePtr, true));
378 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | 206 unsigned FramePtr) const {
239 if (HasFP && (FramePtr == Reg || Reg == AArch64::LR)) {
400 unsigned FramePtr = RegInfo->getFrameRegister(MF);
469 unsigned Reg = RegInfo->getDwarfRegNum(FramePtr, true);
500 emitCalleeSavedFrameMoves(MBB, MBBI, FramePtr);
[all...] |
| AArch64FastISel.cpp | [all...] |
