| /external/vogar/src/vogar/commands/ |
| Rm.java | 23 * A rm command.
25 public final class Rm {
28 public Rm(Log log) {
33 new Command(log, "rm", "-rf", file.getPath()).execute();
|
| /cts/libs/vogar-expect/src/vogar/commands/ |
| Rm.java | 22 * A rm command.
24 public final class Rm {
27 new Command("rm", "-f", file.getPath()).execute();
31 new Command("rm", "-rf", directory.getPath()).execute();
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | [all...] |
| /external/v8/src/arm/ |
| disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm);
194 int rm = instr->RmValue(); local
196 PrintRegister(rm);
199 // Special case for using rm only.
315 } else if (format[1] == 'm') { // 'rm: Rm register
416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) {
423 if (Rm == 15) {
425 } else if (Rm == 13) {
429 "], r%d", Rm);
[all...] |
| simulator-arm.cc | 2010 int rm = instr->RmValue(); local
2090 int rm = instr->RmValue(); local
2218 int rm = instr->RmValue(); local
2239 int rm = instr->RmValue(); local
2718 int rm = instr->RmValue(); local
[all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 153 explicit RmLslImm2(uint32_t instr) : imm2((instr >> 4) & 0x3), rm(instr & 0xf) {}
155 ArmRegister rm; member in struct:art::arm::RmLslImm2
158 os << r.rm;
278 // Show only Rd and Rm.
672 // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm |
681 ArmRegister Rm(instr, 0);
765 args << Rm;
1640 args << rdn << ", " << rm; local
1653 args << DN_Rdn << ", " << rm; local
1664 args << DN_Rdn << ", " << rm; local
1674 args << N_Rn << ", " << rm; local
1682 args << rm; local
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 376 uint32_t Rm;
382 Rm = mAddrMode.reg_imm_Rm;
388 Rm = Op2;
398 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break;
399 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break;
400 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break;
401 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break;
402 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break;
472 int Rm = mAddrMode.reg_imm_Rm;
474 *mPC++ = A64_ADD_X_Wm_SXTW(Rd, Rn, Rm, amount)
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 415 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3)
440 op2 = Rm;
441 regs[Rm] = test.RmValue;
445 op2 = a64asm->reg_imm(Rm, test.shiftMode, test.shiftAmount);
446 regs[Rm] = test.RmValue;
456 case INSTR_MUL: a64asm->MUL(test.cond, test.setFlags, Rd,Rm,Rs); break;
457 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break;
461 case INSTR_SMULBB:a64asm->SMULBB(test.cond, Rd,Rm,Rs); break;
462 case INSTR_SMULBT:a64asm->SMULBT(test.cond, Rd,Rm,Rs); break;
463 case INSTR_SMULTB:a64asm->SMULTB(test.cond, Rd,Rm,Rs); break
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/lldb/source/Plugins/Instruction/ARM/ |
| EmulateInstructionARM.cpp | 739 uint32_t Rm; // the source register
745 Rm = Bits32(opcode, 6, 3);
752 Rm = Bits32(opcode, 5, 3);
759 Rm = Bits32(opcode, 3, 0);
762 if (setflags && (BadReg(Rd) || BadReg(Rm)))
765 if (!setflags && (Rd == 15 || Rm == 15 || (Rd == 13 && Rm == 13)))
770 Rm = Bits32(opcode, 3, 0);
780 uint32_t result = ReadCoreReg(Rm, &success);
784 // The context specifies that Rm is to be moved into Rd
[all...] |
