| /external/llvm/lib/CodeGen/ |
| LiveIntervalUnion.cpp | 150 LiveInterval *VReg = LiveUnionI.value();
151 if (VReg != RecentReg && !isSeenInterference(VReg)) {
152 RecentReg = VReg;
153 InterferingVRegs.push_back(VReg);
|
| CallingConvLower.cpp | 245 unsigned VReg = MF.addLiveIn(PReg, RC);
246 Forwards.push_back(ForwardedRegister(VReg, PReg, RegVT));
|
| LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 LiveInterval &LI = LIS.createEmptyInterval(VReg);
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
46 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
48 return VReg;
387 LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
392 NewRegs.push_back(VReg);
|
| MachineFunction.cpp | 438 unsigned VReg = MRI.getLiveInVirtReg(PReg);
439 if (VReg) {
440 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
450 return VReg;
452 VReg = MRI.createVirtualRegister(RC);
453 MRI.addLiveIn(PReg, VReg);
454 return VReg;
[all...] |
| TailDuplication.cpp | 246 unsigned VReg = SSAUpdateVRs[i];
247 SSAUpdate.Initialize(VReg);
251 MachineInstr *DefMI = MRI->getVRegDef(VReg);
255 SSAUpdate.AddAvailableValue(DefBB, VReg);
260 SSAUpdateVals.find(VReg);
268 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
[all...] |
| RegAllocPBQP.cpp | 125 /// \brief Finds the initial set of vreg intervals to allocate.
131 /// \brief Spill the given VReg.
132 void spillVReg(unsigned VReg, SmallVectorImpl<unsigned> &NewIntervals,
297 unsigned VReg = G.getNodeMetadata(NId).getVReg();
298 LiveInterval &LI = LIS.getInterval(VReg);
565 unsigned VReg = Worklist.back();
568 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
569 LiveInterval &VRegLI = LIS.getInterval(VReg);
575 // Compute an initial allowed set for the current vreg.
606 spillVReg(VReg, NewVRegs, MF, LIS, VRM, VRegSpiller)
[all...] |
| /external/llvm/lib/Target/NVPTX/InstPrinter/ |
| NVPTXInstPrinter.cpp | 66 unsigned VReg = RegNo & 0x0FFFFFFF;
67 OS << VReg;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 100 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
101 // the CopyToReg'd destination register instead of creating a new vreg.
217 // is a vreg in the same register class, use the CopyToReg'd destination
218 // register instead of creating a new vreg.
288 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
291 if (!VReg) {
294 VReg = MRI->createVirtualRegister(RC);
297 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
298 return VReg;
321 unsigned VReg = getVR(Op, VRBaseMap)
[all...] |
| SelectionDAGISel.cpp | 491 DEBUG(dbgs() << "Dropping debug info for dead vreg"
495 // If Reg is live-in then update debug info to track its copy in a vreg.
513 // If this vreg is directly copied into an exported register then
637 // If this is a CopyToReg with a vreg dest, process it.
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 221 unsigned VReg = RegInfo.createVirtualRegister(&BPF::GPRRegClass);
222 RegInfo.addLiveIn(VA.getLocReg(), VReg);
223 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT);
546 // control-flow pattern. The incoming instruction knows the destination vreg
|
| /external/llvm/include/llvm/CodeGen/ |
| CallingConvLower.h | 165 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
166 : VReg(VReg), PReg(PReg), VT(VT) {}
167 unsigned VReg;
|
| RegAllocPBQP.h | 79 /// \brief Holds a vector of the allowed physical regs for a vreg.
154 void setNodeIdForVReg(unsigned VReg, GraphBase::NodeId NId) {
155 VRegToNodeId[VReg] = NId;
158 GraphBase::NodeId getNodeIdForVReg(unsigned VReg) const {
159 auto VRegItr = VRegToNodeId.find(VReg);
165 void eraseNodeIdForVReg(unsigned VReg) {
166 VRegToNodeId.erase(VReg);
195 VReg(0)
205 OptUnsafeEdges(new unsigned[NumOpts]), VReg(Other.VReg),
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 468 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass);
469 RegInfo.addLiveIn(VA.getLocReg(), VReg);
470 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 885 unsigned VReg
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 404 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
405 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
406 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
516 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
517 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
518 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
566 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
568 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
638 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 740 unsigned VReg = MRI.createVirtualRegister(RC);
741 MRI.addLiveIn(VA.getLocReg(), VReg);
742 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
791 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
793 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
