1 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the PowerPC implementation of the TargetRegisterInfo 11 // class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "PPCRegisterInfo.h" 16 #include "PPC.h" 17 #include "PPCFrameLowering.h" 18 #include "PPCInstrBuilder.h" 19 #include "PPCMachineFunctionInfo.h" 20 #include "PPCSubtarget.h" 21 #include "PPCTargetMachine.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineModuleInfo.h" 28 #include "llvm/CodeGen/MachineRegisterInfo.h" 29 #include "llvm/CodeGen/RegisterScavenging.h" 30 #include "llvm/IR/CallingConv.h" 31 #include "llvm/IR/Constants.h" 32 #include "llvm/IR/Function.h" 33 #include "llvm/IR/Type.h" 34 #include "llvm/Support/CommandLine.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/MathExtras.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/Target/TargetFrameLowering.h" 40 #include "llvm/Target/TargetInstrInfo.h" 41 #include "llvm/Target/TargetMachine.h" 42 #include "llvm/Target/TargetOptions.h" 43 #include <cstdlib> 44 45 using namespace llvm; 46 47 #define DEBUG_TYPE "reginfo" 48 49 #define GET_REGINFO_TARGET_DESC 50 #include "PPCGenRegisterInfo.inc" 51 52 static cl::opt<bool> 53 EnableBasePointer("ppc-use-base-pointer", cl::Hidden, cl::init(true), 54 cl::desc("Enable use of a base pointer for complex stack frames")); 55 56 static cl::opt<bool> 57 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false), 58 cl::desc("Force the use of a base pointer in every function")); 59 60 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM) 61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, 62 TM.isPPC64() ? 0 : 1, 63 TM.isPPC64() ? 0 : 1), 64 TM(TM) { 65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; 66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; 67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; 68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; 69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; 70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; 71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; 72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; 73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; 74 75 // 64-bit 76 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; 77 ImmToIdxMap[PPC::LHZ8] = PPC::LHZX8; ImmToIdxMap[PPC::LWZ8] = PPC::LWZX8; 78 ImmToIdxMap[PPC::STB8] = PPC::STBX8; ImmToIdxMap[PPC::STH8] = PPC::STHX8; 79 ImmToIdxMap[PPC::STW8] = PPC::STWX8; ImmToIdxMap[PPC::STDU] = PPC::STDUX; 80 ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; 81 } 82 83 /// getPointerRegClass - Return the register class to use to hold pointers. 84 /// This is used for addressing modes. 85 const TargetRegisterClass * 86 PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 87 const { 88 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value 89 // when it checks for ZERO folding. 90 if (Kind == 1) { 91 if (TM.isPPC64()) 92 return &PPC::G8RC_NOX0RegClass; 93 return &PPC::GPRC_NOR0RegClass; 94 } 95 96 if (TM.isPPC64()) 97 return &PPC::G8RCRegClass; 98 return &PPC::GPRCRegClass; 99 } 100 101 const MCPhysReg* 102 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 103 const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>(); 104 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) { 105 if (Subtarget.hasVSX()) 106 return CSR_64_AllRegs_VSX_SaveList; 107 if (Subtarget.hasAltivec()) 108 return CSR_64_AllRegs_Altivec_SaveList; 109 return CSR_64_AllRegs_SaveList; 110 } 111 112 if (Subtarget.isDarwinABI()) 113 return TM.isPPC64() 114 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList 115 : CSR_Darwin64_SaveList) 116 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList 117 : CSR_Darwin32_SaveList); 118 119 // On PPC64, we might need to save r2 (but only if it is not reserved). 120 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); 121 122 return TM.isPPC64() 123 ? (Subtarget.hasAltivec() 124 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList 125 : CSR_SVR464_Altivec_SaveList) 126 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList)) 127 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList 128 : CSR_SVR432_SaveList); 129 } 130 131 const uint32_t * 132 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, 133 CallingConv::ID CC) const { 134 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 135 if (CC == CallingConv::AnyReg) { 136 if (Subtarget.hasVSX()) 137 return CSR_64_AllRegs_VSX_RegMask; 138 if (Subtarget.hasAltivec()) 139 return CSR_64_AllRegs_Altivec_RegMask; 140 return CSR_64_AllRegs_RegMask; 141 } 142 143 if (Subtarget.isDarwinABI()) 144 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask 145 : CSR_Darwin64_RegMask) 146 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask 147 : CSR_Darwin32_RegMask); 148 149 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask 150 : CSR_SVR464_RegMask) 151 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask 152 : CSR_SVR432_RegMask); 153 } 154 155 const uint32_t* 156 PPCRegisterInfo::getNoPreservedMask() const { 157 return CSR_NoRegs_RegMask; 158 } 159 160 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const { 161 for (unsigned PseudoReg : {PPC::ZERO, PPC::ZERO8, PPC::RM}) 162 Mask[PseudoReg / 32] &= ~(1u << (PseudoReg % 32)); 163 } 164 165 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { 166 BitVector Reserved(getNumRegs()); 167 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 168 const PPCFrameLowering *PPCFI = 169 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering()); 170 171 // The ZERO register is not really a register, but the representation of r0 172 // when used in instructions that treat r0 as the constant 0. 173 Reserved.set(PPC::ZERO); 174 Reserved.set(PPC::ZERO8); 175 176 // The FP register is also not really a register, but is the representation 177 // of the frame pointer register used by ISD::FRAMEADDR. 178 Reserved.set(PPC::FP); 179 Reserved.set(PPC::FP8); 180 181 // The BP register is also not really a register, but is the representation 182 // of the base pointer register used by setjmp. 183 Reserved.set(PPC::BP); 184 Reserved.set(PPC::BP8); 185 186 // The counter registers must be reserved so that counter-based loops can 187 // be correctly formed (and the mtctr instructions are not DCE'd). 188 Reserved.set(PPC::CTR); 189 Reserved.set(PPC::CTR8); 190 191 Reserved.set(PPC::R1); 192 Reserved.set(PPC::LR); 193 Reserved.set(PPC::LR8); 194 Reserved.set(PPC::RM); 195 196 if (!Subtarget.isDarwinABI() || !Subtarget.hasAltivec()) 197 Reserved.set(PPC::VRSAVE); 198 199 // The SVR4 ABI reserves r2 and r13 200 if (Subtarget.isSVR4ABI()) { 201 Reserved.set(PPC::R2); // System-reserved register 202 Reserved.set(PPC::R13); // Small Data Area pointer register 203 } 204 205 // On PPC64, r13 is the thread pointer. Never allocate this register. 206 if (TM.isPPC64()) { 207 Reserved.set(PPC::R13); 208 209 Reserved.set(PPC::X1); 210 Reserved.set(PPC::X13); 211 212 if (PPCFI->needsFP(MF)) 213 Reserved.set(PPC::X31); 214 215 if (hasBasePointer(MF)) 216 Reserved.set(PPC::X30); 217 218 // The 64-bit SVR4 ABI reserves r2 for the TOC pointer. 219 if (Subtarget.isSVR4ABI()) { 220 // We only reserve r2 if we need to use the TOC pointer. If we have no 221 // explicit uses of the TOC pointer (meaning we're a leaf function with 222 // no constant-pool loads, etc.) and we have no potential uses inside an 223 // inline asm block, then we can treat r2 has an ordinary callee-saved 224 // register. 225 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 226 if (FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm()) 227 Reserved.set(PPC::X2); 228 else 229 Reserved.reset(PPC::R2); 230 } 231 } 232 233 if (PPCFI->needsFP(MF)) 234 Reserved.set(PPC::R31); 235 236 if (hasBasePointer(MF)) { 237 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && 238 TM.getRelocationModel() == Reloc::PIC_) 239 Reserved.set(PPC::R29); 240 else 241 Reserved.set(PPC::R30); 242 } 243 244 if (Subtarget.isSVR4ABI() && !TM.isPPC64() && 245 TM.getRelocationModel() == Reloc::PIC_) 246 Reserved.set(PPC::R30); 247 248 // Reserve Altivec registers when Altivec is unavailable. 249 if (!Subtarget.hasAltivec()) 250 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(), 251 IE = PPC::VRRCRegClass.end(); I != IE; ++I) 252 Reserved.set(*I); 253 254 return Reserved; 255 } 256 257 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 258 MachineFunction &MF) const { 259 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 260 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); 261 const unsigned DefaultSafety = 1; 262 263 switch (RC->getID()) { 264 default: 265 return 0; 266 case PPC::G8RC_NOX0RegClassID: 267 case PPC::GPRC_NOR0RegClassID: 268 case PPC::G8RCRegClassID: 269 case PPC::GPRCRegClassID: { 270 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 271 return 32 - FP - DefaultSafety; 272 } 273 case PPC::F8RCRegClassID: 274 case PPC::F4RCRegClassID: 275 case PPC::QFRCRegClassID: 276 case PPC::QSRCRegClassID: 277 case PPC::QBRCRegClassID: 278 case PPC::VRRCRegClassID: 279 case PPC::VFRCRegClassID: 280 case PPC::VSLRCRegClassID: 281 case PPC::VSHRCRegClassID: 282 return 32 - DefaultSafety; 283 case PPC::VSRCRegClassID: 284 case PPC::VSFRCRegClassID: 285 return 64 - DefaultSafety; 286 case PPC::CRRCRegClassID: 287 return 8 - DefaultSafety; 288 } 289 } 290 291 const TargetRegisterClass * 292 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, 293 const MachineFunction &MF) const { 294 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 295 if (Subtarget.hasVSX()) { 296 // With VSX, we can inflate various sub-register classes to the full VSX 297 // register set. 298 299 if (RC == &PPC::F8RCRegClass) 300 return &PPC::VSFRCRegClass; 301 else if (RC == &PPC::VRRCRegClass) 302 return &PPC::VSRCRegClass; 303 } 304 305 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF); 306 } 307 308 //===----------------------------------------------------------------------===// 309 // Stack Frame Processing methods 310 //===----------------------------------------------------------------------===// 311 312 /// lowerDynamicAlloc - Generate the code for allocating an object in the 313 /// current frame. The sequence of code with be in the general form 314 /// 315 /// addi R0, SP, \#frameSize ; get the address of the previous frame 316 /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size 317 /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation 318 /// 319 void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { 320 // Get the instruction. 321 MachineInstr &MI = *II; 322 // Get the instruction's basic block. 323 MachineBasicBlock &MBB = *MI.getParent(); 324 // Get the basic block's function. 325 MachineFunction &MF = *MBB.getParent(); 326 // Get the frame info. 327 MachineFrameInfo *MFI = MF.getFrameInfo(); 328 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 329 // Get the instruction info. 330 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 331 // Determine whether 64-bit pointers are used. 332 bool LP64 = TM.isPPC64(); 333 DebugLoc dl = MI.getDebugLoc(); 334 335 // Get the maximum call stack size. 336 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 337 // Get the total frame size. 338 unsigned FrameSize = MFI->getStackSize(); 339 340 // Get stack alignments. 341 unsigned TargetAlign = Subtarget.getFrameLowering()->getStackAlignment(); 342 unsigned MaxAlign = MFI->getMaxAlignment(); 343 assert((maxCallFrameSize & (MaxAlign-1)) == 0 && 344 "Maximum call-frame size not sufficiently aligned"); 345 346 // Determine the previous frame's address. If FrameSize can't be 347 // represented as 16 bits or we need special alignment, then we load the 348 // previous frame's address from 0(SP). Why not do an addis of the hi? 349 // Because R0 is our only safe tmp register and addi/addis treat R0 as zero. 350 // Constructing the constant and adding would take 3 instructions. 351 // Fortunately, a frame greater than 32K is rare. 352 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 353 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 354 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 355 356 if (MaxAlign < TargetAlign && isInt<16>(FrameSize)) { 357 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg) 358 .addReg(PPC::R31) 359 .addImm(FrameSize); 360 } else if (LP64) { 361 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg) 362 .addImm(0) 363 .addReg(PPC::X1); 364 } else { 365 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg) 366 .addImm(0) 367 .addReg(PPC::R1); 368 } 369 370 bool KillNegSizeReg = MI.getOperand(1).isKill(); 371 unsigned NegSizeReg = MI.getOperand(1).getReg(); 372 373 // Grow the stack and update the stack pointer link, then determine the 374 // address of new allocated space. 375 if (LP64) { 376 if (MaxAlign > TargetAlign) { 377 unsigned UnalNegSizeReg = NegSizeReg; 378 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 379 380 // Unfortunately, there is no andi, only andi., and we can't insert that 381 // here because we might clobber cr0 while it is live. 382 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) 383 .addImm(~(MaxAlign-1)); 384 385 unsigned NegSizeReg1 = NegSizeReg; 386 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); 387 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) 388 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 389 .addReg(NegSizeReg1, RegState::Kill); 390 KillNegSizeReg = true; 391 } 392 393 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) 394 .addReg(Reg, RegState::Kill) 395 .addReg(PPC::X1) 396 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 397 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 398 .addReg(PPC::X1) 399 .addImm(maxCallFrameSize); 400 } else { 401 if (MaxAlign > TargetAlign) { 402 unsigned UnalNegSizeReg = NegSizeReg; 403 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 404 405 // Unfortunately, there is no andi, only andi., and we can't insert that 406 // here because we might clobber cr0 while it is live. 407 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg) 408 .addImm(~(MaxAlign-1)); 409 410 unsigned NegSizeReg1 = NegSizeReg; 411 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); 412 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg) 413 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) 414 .addReg(NegSizeReg1, RegState::Kill); 415 KillNegSizeReg = true; 416 } 417 418 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) 419 .addReg(Reg, RegState::Kill) 420 .addReg(PPC::R1) 421 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); 422 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 423 .addReg(PPC::R1) 424 .addImm(maxCallFrameSize); 425 } 426 427 // Discard the DYNALLOC instruction. 428 MBB.erase(II); 429 } 430 431 /// lowerCRSpilling - Generate the code for spilling a CR register. Instead of 432 /// reserving a whole register (R0), we scrounge for one here. This generates 433 /// code like this: 434 /// 435 /// mfcr rA ; Move the conditional register into GPR rA. 436 /// rlwinm rA, rA, SB, 0, 31 ; Shift the bits left so they are in CR0's slot. 437 /// stw rA, FI ; Store rA to the frame. 438 /// 439 void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, 440 unsigned FrameIndex) const { 441 // Get the instruction. 442 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 443 // Get the instruction's basic block. 444 MachineBasicBlock &MBB = *MI.getParent(); 445 MachineFunction &MF = *MBB.getParent(); 446 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 447 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 448 DebugLoc dl = MI.getDebugLoc(); 449 450 bool LP64 = TM.isPPC64(); 451 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 452 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 453 454 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 455 unsigned SrcReg = MI.getOperand(0).getReg(); 456 457 // We need to store the CR in the low 4-bits of the saved value. First, issue 458 // an MFOCRF to save all of the CRBits and, if needed, kill the SrcReg. 459 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 460 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 461 462 // If the saved register wasn't CR0, shift the bits left so that they are in 463 // CR0's slot. 464 if (SrcReg != PPC::CR0) { 465 unsigned Reg1 = Reg; 466 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 467 468 // rlwinm rA, rA, ShiftBits, 0, 31. 469 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 470 .addReg(Reg1, RegState::Kill) 471 .addImm(getEncodingValue(SrcReg) * 4) 472 .addImm(0) 473 .addImm(31); 474 } 475 476 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 477 .addReg(Reg, RegState::Kill), 478 FrameIndex); 479 480 // Discard the pseudo instruction. 481 MBB.erase(II); 482 } 483 484 void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, 485 unsigned FrameIndex) const { 486 // Get the instruction. 487 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CR <offset> 488 // Get the instruction's basic block. 489 MachineBasicBlock &MBB = *MI.getParent(); 490 MachineFunction &MF = *MBB.getParent(); 491 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 492 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 493 DebugLoc dl = MI.getDebugLoc(); 494 495 bool LP64 = TM.isPPC64(); 496 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 497 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 498 499 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 500 unsigned DestReg = MI.getOperand(0).getReg(); 501 assert(MI.definesRegister(DestReg) && 502 "RESTORE_CR does not define its destination"); 503 504 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 505 Reg), FrameIndex); 506 507 // If the reloaded register isn't CR0, shift the bits right so that they are 508 // in the right CR's slot. 509 if (DestReg != PPC::CR0) { 510 unsigned Reg1 = Reg; 511 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 512 513 unsigned ShiftBits = getEncodingValue(DestReg)*4; 514 // rlwinm r11, r11, 32-ShiftBits, 0, 31. 515 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 516 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) 517 .addImm(31); 518 } 519 520 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg) 521 .addReg(Reg, RegState::Kill); 522 523 // Discard the pseudo instruction. 524 MBB.erase(II); 525 } 526 527 void PPCRegisterInfo::lowerCRBitSpilling(MachineBasicBlock::iterator II, 528 unsigned FrameIndex) const { 529 // Get the instruction. 530 MachineInstr &MI = *II; // ; SPILL_CRBIT <SrcReg>, <offset> 531 // Get the instruction's basic block. 532 MachineBasicBlock &MBB = *MI.getParent(); 533 MachineFunction &MF = *MBB.getParent(); 534 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 535 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 536 DebugLoc dl = MI.getDebugLoc(); 537 538 bool LP64 = TM.isPPC64(); 539 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 540 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 541 542 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 543 unsigned SrcReg = MI.getOperand(0).getReg(); 544 545 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), 546 getCRFromCRBit(SrcReg)) 547 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 548 549 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) 550 .addReg(getCRFromCRBit(SrcReg)); 551 552 // If the saved register wasn't CR0LT, shift the bits left so that the bit to 553 // store is the first one. Mask all but that bit. 554 unsigned Reg1 = Reg; 555 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 556 557 // rlwinm rA, rA, ShiftBits, 0, 0. 558 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg) 559 .addReg(Reg1, RegState::Kill) 560 .addImm(getEncodingValue(SrcReg)) 561 .addImm(0).addImm(0); 562 563 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::STW8 : PPC::STW)) 564 .addReg(Reg, RegState::Kill), 565 FrameIndex); 566 567 // Discard the pseudo instruction. 568 MBB.erase(II); 569 } 570 571 void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, 572 unsigned FrameIndex) const { 573 // Get the instruction. 574 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_CRBIT <offset> 575 // Get the instruction's basic block. 576 MachineBasicBlock &MBB = *MI.getParent(); 577 MachineFunction &MF = *MBB.getParent(); 578 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 579 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 580 DebugLoc dl = MI.getDebugLoc(); 581 582 bool LP64 = TM.isPPC64(); 583 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 584 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 585 586 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 587 unsigned DestReg = MI.getOperand(0).getReg(); 588 assert(MI.definesRegister(DestReg) && 589 "RESTORE_CRBIT does not define its destination"); 590 591 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), 592 Reg), FrameIndex); 593 594 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); 595 596 unsigned RegO = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); 597 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) 598 .addReg(getCRFromCRBit(DestReg)); 599 600 unsigned ShiftBits = getEncodingValue(DestReg); 601 // rlwimi r11, r10, 32-ShiftBits, ..., ... 602 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO) 603 .addReg(RegO, RegState::Kill).addReg(Reg, RegState::Kill) 604 .addImm(ShiftBits ? 32-ShiftBits : 0) 605 .addImm(ShiftBits).addImm(ShiftBits); 606 607 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), 608 getCRFromCRBit(DestReg)) 609 .addReg(RegO, RegState::Kill) 610 // Make sure we have a use dependency all the way through this 611 // sequence of instructions. We can't have the other bits in the CR 612 // modified in between the mfocrf and the mtocrf. 613 .addReg(getCRFromCRBit(DestReg), RegState::Implicit); 614 615 // Discard the pseudo instruction. 616 MBB.erase(II); 617 } 618 619 void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, 620 unsigned FrameIndex) const { 621 // Get the instruction. 622 MachineInstr &MI = *II; // ; SPILL_VRSAVE <SrcReg>, <offset> 623 // Get the instruction's basic block. 624 MachineBasicBlock &MBB = *MI.getParent(); 625 MachineFunction &MF = *MBB.getParent(); 626 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 627 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 628 DebugLoc dl = MI.getDebugLoc(); 629 630 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 631 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 632 unsigned SrcReg = MI.getOperand(0).getReg(); 633 634 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg) 635 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 636 637 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::STW)) 638 .addReg(Reg, RegState::Kill), 639 FrameIndex); 640 641 // Discard the pseudo instruction. 642 MBB.erase(II); 643 } 644 645 void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, 646 unsigned FrameIndex) const { 647 // Get the instruction. 648 MachineInstr &MI = *II; // ; <DestReg> = RESTORE_VRSAVE <offset> 649 // Get the instruction's basic block. 650 MachineBasicBlock &MBB = *MI.getParent(); 651 MachineFunction &MF = *MBB.getParent(); 652 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 653 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 654 DebugLoc dl = MI.getDebugLoc(); 655 656 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 657 unsigned Reg = MF.getRegInfo().createVirtualRegister(GPRC); 658 unsigned DestReg = MI.getOperand(0).getReg(); 659 assert(MI.definesRegister(DestReg) && 660 "RESTORE_VRSAVE does not define its destination"); 661 662 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ), 663 Reg), FrameIndex); 664 665 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg) 666 .addReg(Reg, RegState::Kill); 667 668 // Discard the pseudo instruction. 669 MBB.erase(II); 670 } 671 672 bool 673 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 674 unsigned Reg, int &FrameIdx) const { 675 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 676 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4 677 // ABI, return true to prevent allocating an additional frame slot. 678 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0 679 // is arbitrary and will be subsequently ignored. For 32-bit, we have 680 // previously created the stack slot if needed, so return its FrameIdx. 681 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) { 682 if (TM.isPPC64()) 683 FrameIdx = 0; 684 else { 685 const PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 686 FrameIdx = FI->getCRSpillFrameIndex(); 687 } 688 return true; 689 } 690 return false; 691 } 692 693 // Figure out if the offset in the instruction must be a multiple of 4. 694 // This is true for instructions like "STD". 695 static bool usesIXAddr(const MachineInstr &MI) { 696 unsigned OpC = MI.getOpcode(); 697 698 switch (OpC) { 699 default: 700 return false; 701 case PPC::LWA: 702 case PPC::LWA_32: 703 case PPC::LD: 704 case PPC::STD: 705 return true; 706 } 707 } 708 709 // Return the OffsetOperandNo given the FIOperandNum (and the instruction). 710 static unsigned getOffsetONFromFION(const MachineInstr &MI, 711 unsigned FIOperandNum) { 712 // Take into account whether it's an add or mem instruction 713 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2; 714 if (MI.isInlineAsm()) 715 OffsetOperandNo = FIOperandNum - 1; 716 else if (MI.getOpcode() == TargetOpcode::STACKMAP || 717 MI.getOpcode() == TargetOpcode::PATCHPOINT) 718 OffsetOperandNo = FIOperandNum + 1; 719 720 return OffsetOperandNo; 721 } 722 723 void 724 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 725 int SPAdj, unsigned FIOperandNum, 726 RegScavenger *RS) const { 727 assert(SPAdj == 0 && "Unexpected"); 728 729 // Get the instruction. 730 MachineInstr &MI = *II; 731 // Get the instruction's basic block. 732 MachineBasicBlock &MBB = *MI.getParent(); 733 // Get the basic block's function. 734 MachineFunction &MF = *MBB.getParent(); 735 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 736 // Get the instruction info. 737 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 738 // Get the frame info. 739 MachineFrameInfo *MFI = MF.getFrameInfo(); 740 DebugLoc dl = MI.getDebugLoc(); 741 742 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 743 744 // Get the frame index. 745 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 746 747 // Get the frame pointer save index. Users of this index are primarily 748 // DYNALLOC instructions. 749 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 750 int FPSI = FI->getFramePointerSaveIndex(); 751 // Get the instruction opcode. 752 unsigned OpC = MI.getOpcode(); 753 754 // Special case for dynamic alloca. 755 if (FPSI && FrameIndex == FPSI && 756 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { 757 lowerDynamicAlloc(II); 758 return; 759 } 760 761 // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. 762 if (OpC == PPC::SPILL_CR) { 763 lowerCRSpilling(II, FrameIndex); 764 return; 765 } else if (OpC == PPC::RESTORE_CR) { 766 lowerCRRestore(II, FrameIndex); 767 return; 768 } else if (OpC == PPC::SPILL_CRBIT) { 769 lowerCRBitSpilling(II, FrameIndex); 770 return; 771 } else if (OpC == PPC::RESTORE_CRBIT) { 772 lowerCRBitRestore(II, FrameIndex); 773 return; 774 } else if (OpC == PPC::SPILL_VRSAVE) { 775 lowerVRSAVESpilling(II, FrameIndex); 776 return; 777 } else if (OpC == PPC::RESTORE_VRSAVE) { 778 lowerVRSAVERestore(II, FrameIndex); 779 return; 780 } 781 782 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). 783 MI.getOperand(FIOperandNum).ChangeToRegister( 784 FrameIndex < 0 ? getBaseRegister(MF) : getFrameRegister(MF), false); 785 786 // Figure out if the offset in the instruction is shifted right two bits. 787 bool isIXAddr = usesIXAddr(MI); 788 789 // If the instruction is not present in ImmToIdxMap, then it has no immediate 790 // form (and must be r+r). 791 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && 792 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); 793 794 // Now add the frame object offset to the offset from r1. 795 int Offset = MFI->getObjectOffset(FrameIndex); 796 Offset += MI.getOperand(OffsetOperandNo).getImm(); 797 798 // If we're not using a Frame Pointer that has been set to the value of the 799 // SP before having the stack size subtracted from it, then add the stack size 800 // to Offset to get the correct offset. 801 // Naked functions have stack size 0, although getStackSize may not reflect that 802 // because we didn't call all the pieces that compute it for naked functions. 803 if (!MF.getFunction()->hasFnAttribute(Attribute::Naked)) { 804 if (!(hasBasePointer(MF) && FrameIndex < 0)) 805 Offset += MFI->getStackSize(); 806 } 807 808 // If we can, encode the offset directly into the instruction. If this is a 809 // normal PPC "ri" instruction, any 16-bit value can be safely encoded. If 810 // this is a PPC64 "ix" instruction, only a 16-bit value with the low two bits 811 // clear can be encoded. This is extremely uncommon, because normally you 812 // only "std" to a stack slot that is at least 4-byte aligned, but it can 813 // happen in invalid code. 814 assert(OpC != PPC::DBG_VALUE && 815 "This should be handled in a target-independent way"); 816 if (!noImmForm && ((isInt<16>(Offset) && (!isIXAddr || (Offset & 3) == 0)) || 817 OpC == TargetOpcode::STACKMAP || 818 OpC == TargetOpcode::PATCHPOINT)) { 819 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 820 return; 821 } 822 823 // The offset doesn't fit into a single register, scavenge one to build the 824 // offset in. 825 826 bool is64Bit = TM.isPPC64(); 827 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 828 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 829 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC; 830 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC), 831 SReg = MF.getRegInfo().createVirtualRegister(RC); 832 833 // Insert a set of rA with the full offset value before the ld, st, or add 834 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi) 835 .addImm(Offset >> 16); 836 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg) 837 .addReg(SRegHi, RegState::Kill) 838 .addImm(Offset); 839 840 // Convert into indexed form of the instruction: 841 // 842 // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0 843 // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0 844 unsigned OperandBase; 845 846 if (noImmForm) 847 OperandBase = 1; 848 else if (OpC != TargetOpcode::INLINEASM) { 849 assert(ImmToIdxMap.count(OpC) && 850 "No indexed form of load or store available!"); 851 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; 852 MI.setDesc(TII.get(NewOpcode)); 853 OperandBase = 1; 854 } else { 855 OperandBase = OffsetOperandNo; 856 } 857 858 unsigned StackReg = MI.getOperand(FIOperandNum).getReg(); 859 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false); 860 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false, false, true); 861 } 862 863 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 864 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 865 const TargetFrameLowering *TFI = Subtarget.getFrameLowering(); 866 867 if (!TM.isPPC64()) 868 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; 869 else 870 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1; 871 } 872 873 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const { 874 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 875 if (!hasBasePointer(MF)) 876 return getFrameRegister(MF); 877 878 if (TM.isPPC64()) 879 return PPC::X30; 880 881 if (Subtarget.isSVR4ABI() && 882 TM.getRelocationModel() == Reloc::PIC_) 883 return PPC::R29; 884 885 return PPC::R30; 886 } 887 888 bool PPCRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 889 if (!EnableBasePointer) 890 return false; 891 if (AlwaysBasePointer) 892 return true; 893 894 // If we need to realign the stack, then the stack pointer can no longer 895 // serve as an offset into the caller's stack space. As a result, we need a 896 // base pointer. 897 return needsStackRealignment(MF); 898 } 899 900 bool PPCRegisterInfo::canRealignStack(const MachineFunction &MF) const { 901 if (MF.getFunction()->hasFnAttribute("no-realign-stack")) 902 return false; 903 904 return true; 905 } 906 907 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 908 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 909 const MachineFrameInfo *MFI = MF.getFrameInfo(); 910 const Function *F = MF.getFunction(); 911 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment(); 912 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 913 F->hasFnAttribute(Attribute::StackAlignment)); 914 915 return requiresRealignment && canRealignStack(MF); 916 } 917 918 /// Returns true if the instruction's frame index 919 /// reference would be better served by a base register other than FP 920 /// or SP. Used by LocalStackFrameAllocation to determine which frame index 921 /// references it should create new base registers for. 922 bool PPCRegisterInfo:: 923 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 924 assert(Offset < 0 && "Local offset must be negative"); 925 926 // It's the load/store FI references that cause issues, as it can be difficult 927 // to materialize the offset if it won't fit in the literal field. Estimate 928 // based on the size of the local frame and some conservative assumptions 929 // about the rest of the stack frame (note, this is pre-regalloc, so 930 // we don't know everything for certain yet) whether this offset is likely 931 // to be out of range of the immediate. Return true if so. 932 933 // We only generate virtual base registers for loads and stores that have 934 // an r+i form. Return false for everything else. 935 unsigned OpC = MI->getOpcode(); 936 if (!ImmToIdxMap.count(OpC)) 937 return false; 938 939 // Don't generate a new virtual base register just to add zero to it. 940 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && 941 MI->getOperand(2).getImm() == 0) 942 return false; 943 944 MachineBasicBlock &MBB = *MI->getParent(); 945 MachineFunction &MF = *MBB.getParent(); 946 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 947 const PPCFrameLowering *PPCFI = 948 static_cast<const PPCFrameLowering *>(Subtarget.getFrameLowering()); 949 unsigned StackEst = 950 PPCFI->determineFrameLayout(MF, false, true); 951 952 // If we likely don't need a stack frame, then we probably don't need a 953 // virtual base register either. 954 if (!StackEst) 955 return false; 956 957 // Estimate an offset from the stack pointer. 958 // The incoming offset is relating to the SP at the start of the function, 959 // but when we access the local it'll be relative to the SP after local 960 // allocation, so adjust our SP-relative offset by that allocation size. 961 Offset += StackEst; 962 963 // The frame pointer will point to the end of the stack, so estimate the 964 // offset as the difference between the object offset and the FP location. 965 return !isFrameOffsetLegal(MI, getBaseRegister(MF), Offset); 966 } 967 968 /// Insert defining instruction(s) for BaseReg to 969 /// be a pointer to FrameIdx at the beginning of the basic block. 970 void PPCRegisterInfo:: 971 materializeFrameBaseRegister(MachineBasicBlock *MBB, 972 unsigned BaseReg, int FrameIdx, 973 int64_t Offset) const { 974 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; 975 976 MachineBasicBlock::iterator Ins = MBB->begin(); 977 DebugLoc DL; // Defaults to "unknown" 978 if (Ins != MBB->end()) 979 DL = Ins->getDebugLoc(); 980 981 const MachineFunction &MF = *MBB->getParent(); 982 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 983 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 984 const MCInstrDesc &MCID = TII.get(ADDriOpc); 985 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 986 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 987 988 BuildMI(*MBB, Ins, DL, MCID, BaseReg) 989 .addFrameIndex(FrameIdx).addImm(Offset); 990 } 991 992 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 993 int64_t Offset) const { 994 unsigned FIOperandNum = 0; 995 while (!MI.getOperand(FIOperandNum).isFI()) { 996 ++FIOperandNum; 997 assert(FIOperandNum < MI.getNumOperands() && 998 "Instr doesn't have FrameIndex operand!"); 999 } 1000 1001 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false); 1002 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum); 1003 Offset += MI.getOperand(OffsetOperandNo).getImm(); 1004 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset); 1005 1006 MachineBasicBlock &MBB = *MI.getParent(); 1007 MachineFunction &MF = *MBB.getParent(); 1008 const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); 1009 const TargetInstrInfo &TII = *Subtarget.getInstrInfo(); 1010 const MCInstrDesc &MCID = MI.getDesc(); 1011 MachineRegisterInfo &MRI = MF.getRegInfo(); 1012 MRI.constrainRegClass(BaseReg, 1013 TII.getRegClass(MCID, FIOperandNum, this, MF)); 1014 } 1015 1016 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 1017 unsigned BaseReg, 1018 int64_t Offset) const { 1019 unsigned FIOperandNum = 0; 1020 while (!MI->getOperand(FIOperandNum).isFI()) { 1021 ++FIOperandNum; 1022 assert(FIOperandNum < MI->getNumOperands() && 1023 "Instr doesn't have FrameIndex operand!"); 1024 } 1025 1026 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum); 1027 Offset += MI->getOperand(OffsetOperandNo).getImm(); 1028 1029 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm 1030 MI->getOpcode() == TargetOpcode::STACKMAP || 1031 MI->getOpcode() == TargetOpcode::PATCHPOINT || 1032 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0)); 1033 } 1034 1035
