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      1 //===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 /// \file
     11 /// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #include "AMDGPUSubtarget.h"
     16 #include "R600ISelLowering.h"
     17 #include "R600InstrInfo.h"
     18 #include "R600MachineScheduler.h"
     19 #include "SIISelLowering.h"
     20 #include "SIInstrInfo.h"
     21 #include "SIMachineFunctionInfo.h"
     22 #include "llvm/ADT/SmallString.h"
     23 #include "llvm/CodeGen/MachineScheduler.h"
     24 
     25 using namespace llvm;
     26 
     27 #define DEBUG_TYPE "amdgpu-subtarget"
     28 
     29 #define GET_SUBTARGETINFO_ENUM
     30 #define GET_SUBTARGETINFO_TARGET_DESC
     31 #define GET_SUBTARGETINFO_CTOR
     32 #include "AMDGPUGenSubtargetInfo.inc"
     33 
     34 AMDGPUSubtarget &
     35 AMDGPUSubtarget::initializeSubtargetDependencies(StringRef TT, StringRef GPU,
     36                                                  StringRef FS) {
     37   // Determine default and user-specified characteristics
     38   // On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
     39   // enabled, but some instructions do not respect them and they run at the
     40   // double precision rate, so don't enable by default.
     41   //
     42   // We want to be able to turn these off, but making this a subtarget feature
     43   // for SI has the unhelpful behavior that it unsets everything else if you
     44   // disable it.
     45 
     46   SmallString<256> FullFS("+promote-alloca,+fp64-denormals,");
     47   FullFS += FS;
     48 
     49   if (GPU == "" && Triple(TT).getArch() == Triple::amdgcn)
     50     GPU = "SI";
     51 
     52   ParseSubtargetFeatures(GPU, FullFS);
     53 
     54   // FIXME: I don't think think Evergreen has any useful support for
     55   // denormals, but should be checked. Should we issue a warning somewhere
     56   // if someone tries to enable these?
     57   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
     58     FP32Denormals = false;
     59     FP64Denormals = false;
     60   }
     61   return *this;
     62 }
     63 
     64 AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
     65                                  TargetMachine &TM)
     66     : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU), Is64bit(false),
     67       DumpCode(false), R600ALUInst(false), HasVertexCache(false),
     68       TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
     69       FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
     70       CaymanISA(false), FlatAddressSpace(false), EnableIRStructurizer(true),
     71       EnablePromoteAlloca(false), EnableIfCvt(true), EnableLoadStoreOpt(false),
     72       WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
     73       EnableVGPRSpilling(false), SGPRInitBug(false),
     74       IsGCN(false), GCN1Encoding(false), GCN3Encoding(false),
     75       FrameLowering(TargetFrameLowering::StackGrowsUp,
     76                     64 * 16, // Maximum stack alignment (long16)
     77                     0),
     78       InstrItins(getInstrItineraryForCPU(GPU)), TargetTriple(TT) {
     79 
     80   initializeSubtargetDependencies(TT, GPU, FS);
     81 
     82   if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
     83     InstrInfo.reset(new R600InstrInfo(*this));
     84     TLInfo.reset(new R600TargetLowering(TM, *this));
     85   } else {
     86     InstrInfo.reset(new SIInstrInfo(*this));
     87     TLInfo.reset(new SITargetLowering(TM, *this));
     88   }
     89 }
     90 
     91 unsigned AMDGPUSubtarget::getStackEntrySize() const {
     92   assert(getGeneration() <= NORTHERN_ISLANDS);
     93   switch(getWavefrontSize()) {
     94   case 16:
     95     return 8;
     96   case 32:
     97     return hasCaymanISA() ? 4 : 8;
     98   case 64:
     99     return 4;
    100   default:
    101     llvm_unreachable("Illegal wavefront size.");
    102   }
    103 }
    104 
    105 unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
    106   switch(getGeneration()) {
    107   default: llvm_unreachable("ChipID unknown");
    108   case SEA_ISLANDS: return 12;
    109   }
    110 }
    111 
    112 bool AMDGPUSubtarget::isVGPRSpillingEnabled(
    113                                        const SIMachineFunctionInfo *MFI) const {
    114   return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
    115 }
    116 
    117 void AMDGPUSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
    118                                           MachineInstr *begin,
    119                                           MachineInstr *end,
    120                                           unsigned NumRegionInstrs) const {
    121   if (getGeneration() >= SOUTHERN_ISLANDS) {
    122 
    123     // Track register pressure so the scheduler can try to decrease
    124     // pressure once register usage is above the threshold defined by
    125     // SIRegisterInfo::getRegPressureSetLimit()
    126     Policy.ShouldTrackPressure = true;
    127 
    128     // Enabling both top down and bottom up scheduling seems to give us less
    129     // register spills than just using one of these approaches on its own.
    130     Policy.OnlyTopDown = false;
    131     Policy.OnlyBottomUp = false;
    132   }
    133 }
    134