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      1 //=====-- AMDGPUSubtarget.h - Define Subtarget for the AMDIL ---*- C++ -*-====//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //==-----------------------------------------------------------------------===//
      9 //
     10 /// \file
     11 /// \brief AMDGPU specific subclass of TargetSubtarget.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
     16 #define LLVM_LIB_TARGET_R600_AMDGPUSUBTARGET_H
     17 #include "AMDGPU.h"
     18 #include "AMDGPUFrameLowering.h"
     19 #include "AMDGPUInstrInfo.h"
     20 #include "AMDGPUIntrinsicInfo.h"
     21 #include "AMDGPUSubtarget.h"
     22 #include "R600ISelLowering.h"
     23 #include "llvm/ADT/StringExtras.h"
     24 #include "llvm/ADT/StringRef.h"
     25 #include "llvm/Target/TargetSubtargetInfo.h"
     26 
     27 #define GET_SUBTARGETINFO_HEADER
     28 #include "AMDGPUGenSubtargetInfo.inc"
     29 
     30 namespace llvm {
     31 
     32 class SIMachineFunctionInfo;
     33 
     34 class AMDGPUSubtarget : public AMDGPUGenSubtargetInfo {
     35 
     36 public:
     37   enum Generation {
     38     R600 = 0,
     39     R700,
     40     EVERGREEN,
     41     NORTHERN_ISLANDS,
     42     SOUTHERN_ISLANDS,
     43     SEA_ISLANDS,
     44     VOLCANIC_ISLANDS,
     45   };
     46 
     47   enum {
     48     FIXED_SGPR_COUNT_FOR_INIT_BUG = 80
     49   };
     50 
     51 private:
     52   std::string DevName;
     53   bool Is64bit;
     54   bool DumpCode;
     55   bool R600ALUInst;
     56   bool HasVertexCache;
     57   short TexVTXClauseSize;
     58   Generation Gen;
     59   bool FP64;
     60   bool FP64Denormals;
     61   bool FP32Denormals;
     62   bool FastFMAF32;
     63   bool CaymanISA;
     64   bool FlatAddressSpace;
     65   bool EnableIRStructurizer;
     66   bool EnablePromoteAlloca;
     67   bool EnableIfCvt;
     68   bool EnableLoadStoreOpt;
     69   unsigned WavefrontSize;
     70   bool CFALUBug;
     71   int LocalMemorySize;
     72   bool EnableVGPRSpilling;
     73   bool SGPRInitBug;
     74   bool IsGCN;
     75   bool GCN1Encoding;
     76   bool GCN3Encoding;
     77 
     78   AMDGPUFrameLowering FrameLowering;
     79   std::unique_ptr<AMDGPUTargetLowering> TLInfo;
     80   std::unique_ptr<AMDGPUInstrInfo> InstrInfo;
     81   InstrItineraryData InstrItins;
     82   Triple TargetTriple;
     83 
     84 public:
     85   AMDGPUSubtarget(StringRef TT, StringRef CPU, StringRef FS, TargetMachine &TM);
     86   AMDGPUSubtarget &initializeSubtargetDependencies(StringRef TT, StringRef GPU,
     87                                                    StringRef FS);
     88 
     89   const AMDGPUFrameLowering *getFrameLowering() const override {
     90     return &FrameLowering;
     91   }
     92   const AMDGPUInstrInfo *getInstrInfo() const override {
     93     return InstrInfo.get();
     94   }
     95   const AMDGPURegisterInfo *getRegisterInfo() const override {
     96     return &InstrInfo->getRegisterInfo();
     97   }
     98   AMDGPUTargetLowering *getTargetLowering() const override {
     99     return TLInfo.get();
    100   }
    101   const InstrItineraryData *getInstrItineraryData() const override {
    102     return &InstrItins;
    103   }
    104 
    105   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
    106 
    107   bool is64bit() const {
    108     return Is64bit;
    109   }
    110 
    111   bool hasVertexCache() const {
    112     return HasVertexCache;
    113   }
    114 
    115   short getTexVTXClauseSize() const {
    116     return TexVTXClauseSize;
    117   }
    118 
    119   Generation getGeneration() const {
    120     return Gen;
    121   }
    122 
    123   bool hasHWFP64() const {
    124     return FP64;
    125   }
    126 
    127   bool hasCaymanISA() const {
    128     return CaymanISA;
    129   }
    130 
    131   bool hasFP32Denormals() const {
    132     return FP32Denormals;
    133   }
    134 
    135   bool hasFP64Denormals() const {
    136     return FP64Denormals;
    137   }
    138 
    139   bool hasFastFMAF32() const {
    140     return FastFMAF32;
    141   }
    142 
    143   bool hasFlatAddressSpace() const {
    144     return FlatAddressSpace;
    145   }
    146 
    147   bool hasBFE() const {
    148     return (getGeneration() >= EVERGREEN);
    149   }
    150 
    151   bool hasBFI() const {
    152     return (getGeneration() >= EVERGREEN);
    153   }
    154 
    155   bool hasBFM() const {
    156     return hasBFE();
    157   }
    158 
    159   bool hasBCNT(unsigned Size) const {
    160     if (Size == 32)
    161       return (getGeneration() >= EVERGREEN);
    162 
    163     if (Size == 64)
    164       return (getGeneration() >= SOUTHERN_ISLANDS);
    165 
    166     return false;
    167   }
    168 
    169   bool hasMulU24() const {
    170     return (getGeneration() >= EVERGREEN);
    171   }
    172 
    173   bool hasMulI24() const {
    174     return (getGeneration() >= SOUTHERN_ISLANDS ||
    175             hasCaymanISA());
    176   }
    177 
    178   bool hasFFBL() const {
    179     return (getGeneration() >= EVERGREEN);
    180   }
    181 
    182   bool hasFFBH() const {
    183     return (getGeneration() >= EVERGREEN);
    184   }
    185 
    186   bool IsIRStructurizerEnabled() const {
    187     return EnableIRStructurizer;
    188   }
    189 
    190   bool isPromoteAllocaEnabled() const {
    191     return EnablePromoteAlloca;
    192   }
    193 
    194   bool isIfCvtEnabled() const {
    195     return EnableIfCvt;
    196   }
    197 
    198   bool loadStoreOptEnabled() const {
    199     return EnableLoadStoreOpt;
    200   }
    201 
    202   unsigned getWavefrontSize() const {
    203     return WavefrontSize;
    204   }
    205 
    206   unsigned getStackEntrySize() const;
    207 
    208   bool hasCFAluBug() const {
    209     assert(getGeneration() <= NORTHERN_ISLANDS);
    210     return CFALUBug;
    211   }
    212 
    213   int getLocalMemorySize() const {
    214     return LocalMemorySize;
    215   }
    216 
    217   bool hasSGPRInitBug() const {
    218     return SGPRInitBug;
    219   }
    220 
    221   unsigned getAmdKernelCodeChipID() const;
    222 
    223   bool enableMachineScheduler() const override {
    224     return true;
    225   }
    226 
    227   void overrideSchedPolicy(MachineSchedPolicy &Policy,
    228                            MachineInstr *begin, MachineInstr *end,
    229                            unsigned NumRegionInstrs) const override;
    230 
    231   // Helper functions to simplify if statements
    232   bool isTargetELF() const {
    233     return false;
    234   }
    235 
    236   StringRef getDeviceName() const {
    237     return DevName;
    238   }
    239 
    240   bool dumpCode() const {
    241     return DumpCode;
    242   }
    243   bool r600ALUEncoding() const {
    244     return R600ALUInst;
    245   }
    246   bool isAmdHsaOS() const {
    247     return TargetTriple.getOS() == Triple::AMDHSA;
    248   }
    249   bool isVGPRSpillingEnabled(const SIMachineFunctionInfo *MFI) const;
    250 
    251   unsigned getMaxWavesPerCU() const {
    252     if (getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)
    253       return 10;
    254 
    255     // FIXME: Not sure what this is for other subtagets.
    256     llvm_unreachable("do not know max waves per CU for this subtarget.");
    257   }
    258 
    259   bool enableSubRegLiveness() const override {
    260     return false;
    261   }
    262 };
    263 
    264 } // End namespace llvm
    265 
    266 #endif
    267