| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_screen.h | 50 boolean tiling; member in struct:i915_screen::__anon16367
|
| i915_resource.h | 69 /* tiling flags */
70 enum i915_winsys_buffer_tile tiling; member in struct:i915_texture
|
| i915_resource_texture.c | 178 if (!is->debug.tiling)
216 tex->tiling = I915_TILE_X;
254 tex->tiling = I915_TILE_X;
959 tex->tiling = I915_TILE_NONE;
961 tex->tiling = i915_texture_tiling(is, tex);
982 &tex->tiling, buf_usage);
986 I915_DBG(DBG_TEXTURE, "%s: %p stride %u, blocks (%u, %u) tiling %s\n", __func__,
989 tex->total_nblocksy, get_tiling_string(tex->tiling));
1008 enum i915_winsys_buffer_tile tiling; local
1012 buffer = iws->buffer_from_handle(iws, whandle, &tiling, &stride)
[all...] |
| /external/mesa3d/src/gallium/winsys/i915/sw/ |
| i915_sw_winsys.h | 46 enum i915_winsys_buffer_tile tiling; member in struct:i915_sw_buffer
|
| /hardware/intel/img/psb_video/src/ |
| psb_surface.c | 53 int tiling = GET_SURFACE_INFO_tiling(psb_surface); local
54 if (tiling)
75 if (tiling) {
120 if (tiling) {
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| psb_surface_attrib.c | 116 if (graphic_buffers->tiling)
271 unsigned int tiling
391 psb_surface->extra_info[7] = tiling;
425 unsigned int tiling
529 psb_surface->extra_info[7] = tiling;
771 int tiling; local
775 drv_debug_msg(VIDEO_DEBUG_GENERAL, "Create %d surface(%dx%d) with type %d, tiling is %d\n",
776 num_surfaces, width, height, attribute_tpi->type, attribute_tpi->tiling);
778 tiling = attribute_tpi->tiling;
[all...] |
| psb_drv_video.h | 497 int tiling; member in struct:psb_surface_share_info_s
640 unsigned int tiling; /* the memory is tiling or not */ member in struct:_PsbSurfaceAttributeTPI
|
| /hardware/intel/common/libva/va/ |
| va_tpi.h | 57 unsigned int tiling; /* the memory is tiling or not */ member in struct:_VASurfaceAttributeTPI
|
| /external/mesa3d/src/mesa/drivers/dri/intel/ |
| intel_regions.c | 136 if (region->tiling != I915_TILING_NONE)
156 if (region->tiling != I915_TILING_NONE)
171 uint32_t tiling, drm_intel_bo *buffer)
185 region->tiling = tiling;
194 uint32_t tiling,
208 &tiling, &aligned_pitch, flags);
213 aligned_pitch / cpp, tiling, buffer);
247 uint32_t bit_6_swizzle, tiling; local
266 ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle)
411 uint32_t tiling = region->tiling; local
444 uint32_t tiling = region->tiling; local
[all...] |
| intel_regions.h | 70 uint32_t tiling; /**< Which tiling mode the region is in */ member in struct:intel_region
81 uint32_t tiling,
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| intel_screen.c | 58 DRI_CONF_DESC(en, "Enable texture tiling")
386 uint32_t tiling; local
389 tiling = I915_TILING_X;
393 tiling = I915_TILING_NONE;
399 intel_region_alloc(intelScreen, tiling, cpp, width, height, true);
564 image->region->tiling = parent->region->tiling;
893 uint32_t tiling = I915_TILING_X; local
898 &tiling, &aligned_pitch, flags);
902 drm_intel_bo_get_tiling(buffer, &tiling, &swizzle_mode)
[all...] |
| intel_mipmap_tree.c | 200 uint32_t tiling = I915_TILING_NONE; local
216 tiling = I915_TILING_Y;
224 * Our usual reason for preferring X tiling (fast blits using the
228 * So use Y tiling, since it makes better use of the cache.
230 tiling = I915_TILING_Y;
232 tiling = I915_TILING_X;
255 tiling = I915_TILING_NONE;
262 tiling,
707 0, src_mt->region->tiling,
709 0, dst_mt->region->tiling,
[all...] |
| /external/drm_gralloc/ |
| gralloc_drm_intel.c | 71 uint32_t tiling; member in struct:intel_buffer
243 uint32_t *tiling, unsigned long *stride)
275 *tiling = I915_TILING_X;
278 *tiling = I915_TILING_NONE;
287 bpp, tiling, stride, flags);
294 if (*tiling != I915_TILING_NONE) {
296 *tiling = I915_TILING_NONE;
309 *tiling = I915_TILING_NONE;
313 *tiling = I915_TILING_X;
315 *tiling = I915_TILING_NONE
[all...] |
| gralloc_drm_radeon.c | 81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling)
86 if (tiling & RADEON_TILING_MACRO) {
92 } else if (tiling & RADEON_TILING_MICRO) {
112 if (tiling)
122 static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling)
127 if (tiling & RADEON_TILING_MACRO)
129 else if (tiling & RADEON_TILING_MICRO)
135 if (tiling)
146 int bpe, uint32_t tiling)
148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling);
191 uint32_t tiling, domain; local
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen7_blorp.cpp | 185 uint32_t tiling = surface->map_stencil_as_y_tiled local
186 ? I915_TILING_Y : region->tiling;
187 gen7_set_surface_tiling(surf, tiling);
|
| gen6_blorp.cpp | 446 uint32_t tiling = surface->map_stencil_as_y_tiled local
448 : brw_get_surface_tiling_bits(region->tiling);
452 surf[3] = (tiling |
[all...] |
| /hardware/intel/img/hwcomposer/merrifield/ips/common/ |
| VideoPayloadBuffer.h | 35 int tiling; member in struct:android::intel::VideoPayloadBuffer
|
| /hardware/intel/img/hwcomposer/moorefield_hdmi/ips/common/ |
| VideoPayloadBuffer.h | 35 int tiling; member in struct:android::intel::VideoPayloadBuffer
|
| /external/libdrm/intel/ |
| intel_decode.c | 1790 const char *tiling; local
2165 const char *name, *tiling; local
[all...] |
| intel_bufmgr_gem.c | 169 * Current tiling mode
292 /* 965+ just need multiples of page size for tiling */
321 * Round a given pitch up to the minimum required for X tiling on a
322 * given chip. We use 512 as the minimum to allow for a later tiling
528 /* The older chipsets are far-less flexible in terms of tiling,
820 uint32_t tiling; local
825 tiling = *tiling_mode;
841 if ((bufmgr_gem->gen == 2) && tiling != I915_TILING_NONE)
843 else if (tiling == I915_TILING_X
845 && tiling == I915_TILING_Y)
[all...] |
