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  /build/core/combo/arch/x86/
ivybridge.mk 15 -march=core-avx-i \
sandybridge.mk 15 -march=corei7-avx \
  /build/core/combo/arch/x86_64/
ivybridge.mk 15 -march=core-avx-i
sandybridge.mk 15 -march=corei7-avx
  /external/lldb/tools/debugserver/source/MacOSX/i386/
DNBArchImplI386.cpp 355 m_state.context.fpu.avx.__fpu_reserved[0] = -1;
356 m_state.context.fpu.avx.__fpu_reserved[1] = -1;
357 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
358 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
359 m_state.context.fpu.avx.__fpu_ftw = 1;
360 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
361 m_state.context.fpu.avx.__fpu_fop = 2;
362 m_state.context.fpu.avx.__fpu_ip = 3;
363 m_state.context.fpu.avx.__fpu_cs = 4;
364 m_state.context.fpu.avx.__fpu_rsrv2 = 5
    [all...]
DNBArchImplI386.h 67 typedef __i386_avx_state_t AVX;
99 e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
115 AVX avx; member in union:DNBArchImplI386::Context::__anon14368
  /external/lldb/tools/debugserver/source/MacOSX/x86_64/
DNBArchImplX86_64.cpp 86 // Only xnu-2020 or later has AVX support, any versions before
89 // verify the kernel version number manually or disable AVX support.
264 m_state.context.fpu.avx.__fpu_reserved[0] = -1;
265 m_state.context.fpu.avx.__fpu_reserved[1] = -1;
266 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
267 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
268 m_state.context.fpu.avx.__fpu_ftw = 1;
269 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
270 m_state.context.fpu.avx.__fpu_fop = 2;
271 m_state.context.fpu.avx.__fpu_ip = 3
    [all...]
DNBArchImplX86_64.h 66 typedef __x86_64_avx_state_t AVX;
98 e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
114 AVX avx; member in union:DNBArchImplX86_64::Context::__anon14386
  /external/flac/libFLAC/include/private/
cpu.h 130 FLAC__bool avx; member in struct:__anon9330
142 FLAC__bool avx; member in struct:__anon9331
  /external/flac/libFLAC/
cpu.c 59 info->ia32.avx = false;
68 info->x86.avx = false;
185 info->ia32.avx = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_AVX )? true : false;
203 fprintf(stderr, " AVX ........ %c\n", info->ia32.avx ? 'Y' : 'n');
323 * now have to check for OS support of AVX instructions
325 if(info->ia32.avx && ia32_osxsave) {
330 fprintf(stderr, " AVX OS sup . %c\n", info->ia32.avx ? 'Y' : 'n');
333 else /* no OS AVX support*
    [all...]
  /external/boringssl/src/crypto/sha/asm/
sha256-586.pl 28 # May version, >60% over original. Add AVX+shrd code path, >25%
35 # not shown.) Add AVX+BMI code path.
68 $xmm=$avx=0;
73 $avx = ($1>=2.19) + ($1>=2.22);
76 if ($xmm && !$avx && $ARGV[0] eq "win32n" &&
78 $avx = ($1>=2.03) + ($1>=2.10);
81 if ($xmm && !$avx && $ARGV[0] eq "win32" &&
83 $avx = ($1>=10) + ($1>=11);
86 if ($xmm && !$avx && `$ENV{CC} -v 2>&1` =~ /(^clang version|based on LLVM) ([3-9]\.[0-9]+)/) {
87 $avx = ($2>=3.0) + ($2>3.0)
    [all...]
sha512-x86_64.pl 55 # the effort, not on pre-AVX processors. [Obviously with exclusion
69 # for AVX, but with %ymm as operands. Side effect is increased stack
80 # SHA256 SSSE3 AVX/XOP(*) SHA512 AVX/XOP(*)
114 $avx = ($1>=2.19) + ($1>=2.22);
117 if (!$avx && $win64 && ($flavour =~ /nasm/ || $ENV{ASM} =~ /nasm/) &&
119 $avx = ($1>=2.09) + ($1>=2.10);
122 if (!$avx && $win64 && ($flavour =~ /masm/ || $ENV{ASM} =~ /ml64/) &&
124 $avx = ($1>=10) + ($1>=11);
127 if (!$avx && `$ENV{CC} -v 2>&1` =~ /(^clang version|based on LLVM) ([3-9]\.[0-9]+)/)
    [all...]
sha1-x86_64.pl 50 # Add AVX code path. See sha1-586.pl for further information.
68 # x86_64 SSSE3 AVX[2]
97 $avx = ($1>=2.19) + ($1>=2.22);
100 if (!$avx && $win64 && ($flavour =~ /nasm/ || $ENV{ASM} =~ /nasm/) &&
102 $avx = ($1>=2.09) + ($1>=2.10);
105 if (!$avx && $win64 && ($flavour =~ /masm/ || $ENV{ASM} =~ /ml64/) &&
107 $avx = ($1>=10) + ($1>=11);
110 if (!$avx && `$ENV{CC} -v 2>&1` =~ /(^clang version|based on LLVM) ([2-9]\.[0-9]+)/) {
111 $avx = ($2>=3.0) + ($2>3.0);
115 $avx=1 if (!$shaext && $avx)
    [all...]
  /external/libvpx/libvpx/build/make/
rtcd.pl 361 @ALL_ARCHS = filter(qw/mmx sse sse2 sse3 ssse3 sse4_1 avx avx2/);
364 @ALL_ARCHS = filter(qw/mmx sse sse2 sse3 ssse3 sse4_1 avx avx2/);
gen_msvs_vcxproj.sh 109 # Check for AVX and turn it on to avoid warnings.
110 if [[ $f =~ avx.?\.c$ ]]; then
111 tag_content AdditionalOptions "/arch:AVX"
configure.sh 1117 echo "${tgt_cc} does not support avx/avx2, disabling....."
1118 RTCD_OPTIONS="${RTCD_OPTIONS}--disable-avx --disable-avx2 "
1119 soft_disable avx
1149 check_gcc_machine_option avx
    [all...]
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/build/make/
rtcd.pl 358 @ALL_ARCHS = filter(qw/mmx sse sse2 sse3 ssse3 sse4_1 avx avx2/);
361 @ALL_ARCHS = filter(qw/mmx sse sse2 sse3 ssse3 sse4_1 avx avx2/);
gen_msvs_vcxproj.sh 183 # Check for AVX and turn it on to avoid warnings.
184 if [[ $f =~ avx.?\.c$ ]]; then
185 tag_content AdditionalOptions "/arch:AVX"
configure.sh 1096 echo "${tgt_cc} does not support avx/avx2, disabling....."
1097 RTCD_OPTIONS="${RTCD_OPTIONS}--disable-avx --disable-avx2 "
1098 soft_disable avx
1114 check_gcc_machine_option avx
    [all...]
  /external/boringssl/src/crypto/modes/asm/
aesni-gcm-x86_64.pl 46 $avx = ($1>=2.19) + ($1>=2.22);
49 if (!$avx && $win64 && ($flavour =~ /nasm/ || $ENV{ASM} =~ /nasm/) &&
51 $avx = ($1>=2.09) + ($1>=2.10);
54 if (!$avx && $win64 && ($flavour =~ /masm/ || $ENV{ASM} =~ /ml64/) &&
56 $avx = ($1>=10) + ($1>=11);
59 if (!$avx && `$ENV{CC} -v 2>&1` =~ /(^clang version|based on LLVM) ([3-9]\.[0-9]+)/) {
60 $avx = ($2>=3.0) + ($2>3.0);
66 if ($avx>1) {{{
ghash-x86_64.pl 65 # Haswell 0.55(+93%) (if system doesn't support AVX)
66 # Broadwell 0.45(+110%)(if system doesn't support AVX)
72 # ... 8x aggregate factor AVX code path is using reduction algorithm
73 # suggested by Shay Gueron[1]. Even though contemporary AVX-capable
95 $avx = ($1>=2.19) + ($1>=2.22);
98 if (!$avx && $win64 && ($flavour =~ /nasm/ || $ENV{ASM} =~ /nasm/) &&
100 $avx = ($1>=2.09) + ($1>=2.10);
103 if (!$avx && $win64 && ($flavour =~ /masm/ || $ENV{ASM} =~ /ml64/) &&
105 $avx = ($1>=10) + ($1>=11);
108 if (!$avx && `$ENV{CC} -v 2>&1` =~ /(^clang version|based on LLVM) ([3-9]\.[0-9]+)/)
    [all...]
  /external/boringssl/src/crypto/bn/asm/
rsaz-avx2.pl 84 $avx = ($1>=2.19) + ($1>=2.22);
88 if (!$avx && $win64 && ($flavour =~ /nasm/ || $ENV{ASM} =~ /nasm/) &&
90 $avx = ($1>=2.09) + ($1>=2.10);
94 if (!$avx && $win64 && ($flavour =~ /masm/ || $ENV{ASM} =~ /ml64/) &&
96 $avx = ($1>=10) + ($1>=11);
100 if (!$avx && `$ENV{CC} -v 2>&1` =~ /(^clang version|based on LLVM) ([3-9])\.([0-9]+)/) {
102 $avx = ($ver>=3.0) + ($ver>=3.01);
109 if ($avx>1) {{{
    [all...]
  /external/libvpx/libvpx/third_party/x86inc/
x86inc.asm 707 %if cpuflag(avx)
781 ; FIXME: INIT_AVX can be replaced by INIT_XMM avx
934 ; AVX abstraction layer
993 ; 3arg AVX ops with a memory arg can only have it in src2,
1184 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/third_party/x86inc/
x86inc.asm 686 %if cpuflag(avx)
760 ; FIXME: INIT_AVX can be replaced by INIT_XMM avx
913 ; AVX abstraction layer
972 ; 3arg AVX ops with a memory arg can only have it in src2,
1163 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN

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