| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMBaseInfo.h | 26 namespace ARMCC {
66 } // namespace ARMCC
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
70 case ARMCC::EQ: return "eq";
71 case ARMCC::NE: return "ne";
72 case ARMCC::HS: return "hs";
73 case ARMCC::LO: return "lo";
74 case ARMCC::MI: return "mi";
75 case ARMCC::PL: return "pl";
76 case ARMCC::VS: return "vs"
[all...] |
| ARMMCTargetDesc.cpp | 353 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
360 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
|
| ARMMCCodeEmitter.cpp | 692 if (ARMCC::CondCodes(MCOp1.getImm()) != ARMCC::AL)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ThumbRegisterInfo.h | 43 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
|
| Thumb2ITBlockPass.cpp | 45 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
107 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
155 ARMCC::CondCodes NCC = getITInstrPredicate(I, NPredReg);
172 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
173 if (CC == ARMCC::AL) {
195 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
212 ARMCC::CondCodes NCC = getITInstrPredicate(NMI, NPredReg)
[all...] |
| ARMAsmPrinter.cpp | 137 .addImm(ARMCC::AL)
[all...] |
| Thumb2InstrInfo.h | 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
|
| ARMBaseInstrInfo.h | 129 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
131 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
132 : ARMCC::AL;
386 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
440 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
461 ARMCC::CondCodes Pred, unsigned PredReg,
467 ARMCC::CondCodes Pred, unsigned PredReg,
|
| ARMBaseInstrInfo.cpp | 167 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
416 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
429 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
437 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
438 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
448 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
455 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
486 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm()
[all...] |
| ARMBaseRegisterInfo.h | 163 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
|
| ARMLoadStoreOptimizer.cpp | 104 ARMCC::CondCodes Pred, unsigned PredReg);
107 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
120 ARMCC::CondCodes Pred,
127 ARMCC::CondCodes Pred, unsigned PredReg,
382 ARMCC::CondCodes Pred, unsigned PredReg) {
481 int Opcode, ARMCC::CondCodes Pred,
583 if (Pred != ARMCC::AL)
734 ARMCC::CondCodes Pred, unsigned PredReg,
833 ARMCC::CondCodes Pred, unsigned PredReg,
[all...] |
| Thumb2InstrInfo.cpp | 39 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg);
63 if (CC != ARMCC::AL)
71 if (CC != ARMCC::AL) {
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
223 ARMCC::CondCodes Pred, unsigned PredReg,
461 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
629 ARMCC::CondCodes
633 return ARMCC::AL;
|
| Thumb2SizeReduction.cpp | 154 bool is2Addr, ARMCC::CondCodes Pred,
293 bool is2Addr, ARMCC::CondCodes Pred,
297 if (Pred == ARMCC::AL) {
547 if (MI->getOperand(3).getImm() != ARMCC::AL)
582 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
686 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
688 if (Pred != ARMCC::AL) {
783 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
785 if (Pred != ARMCC::AL) {
[all...] |
| ARMInstrInfo.cpp | 40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
46 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
| ARMConstantIslandPass.cpp | [all...] |
| ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg,
86 ARMCC::CondCodes Pred, unsigned PredReg,
97 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred,
160 ARMCC::AL, 0, MIFlags);
|
| ARMFastISel.cpp | [all...] |
| Thumb1InstrInfo.cpp | 32 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
| ARMFrameLowering.cpp | 119 ARMCC::CondCodes Pred = ARMCC::AL,
133 ARMCC::CondCodes Pred = ARMCC::AL,
454 .addImm((unsigned)ARMCC::AL).addReg(0)
466 .addImm((unsigned)ARMCC::AL).addReg(0)
669 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
716 if (STI.isThumb()) MIB.addImm(ARMCC::AL).addReg(0);
785 ARMCC::AL, 0, TII);
797 ARMCC::AL, 0, TII)
[all...] |
| ARMISelLowering.cpp | [all...] |
| MLxExpansionPass.cpp | 284 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
|
| ARMBaseRegisterInfo.cpp | 395 ARMCC::CondCodes Pred,
745 ARMCC::CondCodes Pred = (PIdx == -1)
746 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
|
| ARMExpandPseudoInsts.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 149 ARMCC::CondCodes Cond; // Condition for IT block.
424 ARMCC::CondCodes Val;
660 ARMCC::CondCodes getCondCode() const {
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 996 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
1000 else if (CC != ARMCC::AL)
1008 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
[all...] |
