1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the base ARM implementation of TargetRegisterInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H 15 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H 16 17 #include "MCTargetDesc/ARMBaseInfo.h" 18 #include "llvm/Target/TargetRegisterInfo.h" 19 20 #define GET_REGINFO_HEADER 21 #include "ARMGenRegisterInfo.inc" 22 23 namespace llvm { 24 /// Register allocation hints. 25 namespace ARMRI { 26 enum { 27 RegPairOdd = 1, 28 RegPairEven = 2 29 }; 30 } 31 32 /// isARMArea1Register - Returns true if the register is a low register (r0-r7) 33 /// or a stack/pc register that we should push/pop. 34 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { 35 using namespace ARM; 36 switch (Reg) { 37 case R0: case R1: case R2: case R3: 38 case R4: case R5: case R6: case R7: 39 case LR: case SP: case PC: 40 return true; 41 case R8: case R9: case R10: case R11: case R12: 42 // For iOS we want r7 and lr to be next to each other. 43 return !isIOS; 44 default: 45 return false; 46 } 47 } 48 49 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { 50 using namespace ARM; 51 switch (Reg) { 52 case R8: case R9: case R10: case R11: case R12: 53 // iOS has this second area. 54 return isIOS; 55 default: 56 return false; 57 } 58 } 59 60 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { 61 using namespace ARM; 62 switch (Reg) { 63 case D15: case D14: case D13: case D12: 64 case D11: case D10: case D9: case D8: 65 return true; 66 default: 67 return false; 68 } 69 } 70 71 static inline bool isCalleeSavedRegister(unsigned Reg, 72 const MCPhysReg *CSRegs) { 73 for (unsigned i = 0; CSRegs[i]; ++i) 74 if (Reg == CSRegs[i]) 75 return true; 76 return false; 77 } 78 79 class ARMBaseRegisterInfo : public ARMGenRegisterInfo { 80 protected: 81 /// BasePtr - ARM physical register used as a base ptr in complex stack 82 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 83 /// variable size stack objects. 84 unsigned BasePtr; 85 86 // Can be only subclassed. 87 explicit ARMBaseRegisterInfo(); 88 89 // Return the opcode that implements 'Op', or 0 if no opcode 90 unsigned getOpcode(int Op) const; 91 92 public: 93 /// Code Generation virtual methods... 94 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override; 95 const uint32_t *getCallPreservedMask(const MachineFunction &MF, 96 CallingConv::ID) const override; 97 const uint32_t *getNoPreservedMask() const; 98 99 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the 100 /// case that 'returned' is on an i32 first argument if the calling convention 101 /// is one that can (partially) model this attribute with a preserved mask 102 /// (i.e. it is a calling convention that uses the same register for the first 103 /// i32 argument and an i32 return value) 104 /// 105 /// Should return NULL in the case that the calling convention does not have 106 /// this property 107 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF, 108 CallingConv::ID) const; 109 110 BitVector getReservedRegs(const MachineFunction &MF) const override; 111 112 const TargetRegisterClass * 113 getPointerRegClass(const MachineFunction &MF, 114 unsigned Kind = 0) const override; 115 const TargetRegisterClass * 116 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 117 118 const TargetRegisterClass * 119 getLargestLegalSuperClass(const TargetRegisterClass *RC, 120 const MachineFunction &MF) const override; 121 122 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 123 MachineFunction &MF) const override; 124 125 void getRegAllocationHints(unsigned VirtReg, 126 ArrayRef<MCPhysReg> Order, 127 SmallVectorImpl<MCPhysReg> &Hints, 128 const MachineFunction &MF, 129 const VirtRegMap *VRM) const override; 130 131 void updateRegAllocHint(unsigned Reg, unsigned NewReg, 132 MachineFunction &MF) const override; 133 134 bool hasBasePointer(const MachineFunction &MF) const; 135 136 bool canRealignStack(const MachineFunction &MF) const; 137 bool needsStackRealignment(const MachineFunction &MF) const override; 138 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, 139 int Idx) const override; 140 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override; 141 void materializeFrameBaseRegister(MachineBasicBlock *MBB, 142 unsigned BaseReg, int FrameIdx, 143 int64_t Offset) const override; 144 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, 145 int64_t Offset) const override; 146 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, 147 int64_t Offset) const override; 148 149 bool cannotEliminateFrame(const MachineFunction &MF) const; 150 151 // Debug information queries. 152 unsigned getFrameRegister(const MachineFunction &MF) const override; 153 unsigned getBaseRegister() const { return BasePtr; } 154 155 bool isLowRegister(unsigned Reg) const; 156 157 158 /// emitLoadConstPool - Emits a load from constpool to materialize the 159 /// specified immediate. 160 virtual void emitLoadConstPool(MachineBasicBlock &MBB, 161 MachineBasicBlock::iterator &MBBI, 162 DebugLoc dl, unsigned DestReg, unsigned SubIdx, 163 int Val, ARMCC::CondCodes Pred = ARMCC::AL, 164 unsigned PredReg = 0, 165 unsigned MIFlags = MachineInstr::NoFlags)const; 166 167 /// Code Generation virtual methods... 168 bool requiresRegisterScavenging(const MachineFunction &MF) const override; 169 170 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override; 171 172 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override; 173 174 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override; 175 176 void eliminateFrameIndex(MachineBasicBlock::iterator II, 177 int SPAdj, unsigned FIOperandNum, 178 RegScavenger *RS = nullptr) const override; 179 180 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true 181 bool shouldCoalesce(MachineInstr *MI, 182 const TargetRegisterClass *SrcRC, 183 unsigned SubReg, 184 const TargetRegisterClass *DstRC, 185 unsigned DstSubReg, 186 const TargetRegisterClass *NewRC) const override; 187 }; 188 189 } // end namespace llvm 190 191 #endif 192
